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TheRock/compiler/amd-llvm/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

50 lines
1.1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define i64 @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $12, 0
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb65
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1: # %bb56
entry:
%t0 = load i32, ptr null, align 8
switch i32 %t0, label %bb65 [
i32 16, label %bb
i32 12, label %bb56
]
bb:
br label %bb65
bb56:
unreachable
bb65:
%a = phi i64 [ 0, %bb ], [ 0, %entry ]
tail call void asm "", "{cx}"(i64 %a) nounwind
%t15 = and i64 %a, 4294967295
ret i64 %t15
}
define i64 @bar(i64 %t0) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: negl %eax
; CHECK-NEXT: retq
call void asm "", "{cx}"(i64 0) nounwind
%t1 = sub i64 0, %t0
%t2 = and i64 %t1, 4294967295
ret i64 %t2
}