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TheRock/compiler/amd-llvm/llvm/test/Instrumentation/MemorySanitizer/Hexagon/vararg-hexagon.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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5.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -S -passes=msan 2>&1 | FileCheck %s
; RUN: opt < %s -S -passes=msan -msan-track-origins=1 2>&1 | FileCheck %s --check-prefixes=ORIGIN
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown-linux-musl"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i32 [[TMP1]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 8 [[TMP2]], i8 0, i32 [[TMP1]], i1 false)
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP1]], i32 800)
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i32 [[TMP3]], i1 false)
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[VL:%.*]] = alloca ptr, align 4
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[VL]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 536870912
; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[TMP6]], i8 0, i32 4, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[VL]])
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[VL]] to i32
; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP7]], 536870912
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP8]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP9]], i8 0, i64 12, i1 false)
; CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VL]])
; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[VL]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = xor i32 [[TMP13]], 536870912
; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i32 [[TMP14]] to ptr
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP15]], ptr align 4 [[TMP2]], i32 [[TMP1]], i1 false)
; CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VL]])
; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[VL]])
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i32 0
;
; ORIGIN-LABEL: define i32 @foo(
; ORIGIN-SAME: i32 [[GUARD:%.*]], ...) {
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
; ORIGIN-NEXT: [[TMP2:%.*]] = alloca i8, i32 [[TMP1]], align 8
; ORIGIN-NEXT: call void @llvm.memset.p0.i32(ptr align 8 [[TMP2]], i8 0, i32 [[TMP1]], i1 false)
; ORIGIN-NEXT: [[TMP3:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP1]], i32 800)
; ORIGIN-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i32 [[TMP3]], i1 false)
; ORIGIN-NEXT: call void @llvm.donothing()
; ORIGIN-NEXT: [[VL:%.*]] = alloca ptr, align 4
; ORIGIN-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[VL]] to i32
; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 536870912
; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
; ORIGIN-NEXT: [[TMP7:%.*]] = add i32 [[TMP5]], 1342177280
; ORIGIN-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], -4
; ORIGIN-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP8]] to ptr
; ORIGIN-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[TMP6]], i8 0, i32 4, i1 false)
; ORIGIN-NEXT: call void @llvm.lifetime.start.p0(ptr [[VL]])
; ORIGIN-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[VL]] to i32
; ORIGIN-NEXT: [[TMP11:%.*]] = xor i32 [[TMP10]], 536870912
; ORIGIN-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP11]] to ptr
; ORIGIN-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], 1342177280
; ORIGIN-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP13]] to ptr
; ORIGIN-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP12]], i8 0, i64 12, i1 false)
; ORIGIN-NEXT: call void @llvm.va_start.p0(ptr [[VL]])
; ORIGIN-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[VL]] to i32
; ORIGIN-NEXT: [[TMP16:%.*]] = inttoptr i32 [[TMP15]] to ptr
; ORIGIN-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
; ORIGIN-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[TMP17]] to i32
; ORIGIN-NEXT: [[TMP19:%.*]] = xor i32 [[TMP18]], 536870912
; ORIGIN-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP19]] to ptr
; ORIGIN-NEXT: [[TMP21:%.*]] = add i32 [[TMP19]], 1342177280
; ORIGIN-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP21]] to ptr
; ORIGIN-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP20]], ptr align 4 [[TMP2]], i32 [[TMP1]], i1 false)
; ORIGIN-NEXT: call void @llvm.va_end.p0(ptr [[VL]])
; ORIGIN-NEXT: call void @llvm.lifetime.end.p0(ptr [[VL]])
; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4
; ORIGIN-NEXT: ret i32 0
;
%vl = alloca ptr, align 4
call void @llvm.lifetime.start.p0(i64 4, ptr %vl)
call void @llvm.va_start(ptr %vl)
call void @llvm.va_end(ptr %vl)
call void @llvm.lifetime.end.p0(i64 4, ptr %vl)
ret i32 0
}
declare void @llvm.lifetime.start.p0(i64, ptr)
declare void @llvm.lifetime.end.p0(i64, ptr)
declare void @llvm.va_start(ptr)
declare void @llvm.va_end(ptr)
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