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TheRock/compiler/amd-llvm/llvm/test/Instrumentation/MemorySanitizer/ftrunc.ll
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2026-09-02 16:34:47 -07:00

323 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s
;
; Forked from llvm/test/Instrumentation/MemorySanitizer/ftrunc.ll
;
; Handled strictly: (none)
;
; Handled heuristically: (none)
;
; REQUIRES: x86-registered-target
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
declare i32 @llvm.fptoui.sat.i32.f32(float)
declare i64 @llvm.fptosi.sat.i64.f64(double)
define float @trunc_unsigned_f32(float %x) #0 {
; CHECK-LABEL: define float @trunc_unsigned_f32(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[I:%.*]] = fptoui float [[X]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[R:%.*]] = uitofp i32 [[I]] to float
; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret float [[R]]
;
%i = fptoui float %x to i32
%r = uitofp i32 %i to float
ret float %r
}
define double @trunc_unsigned_f64(double %x) #0 {
; CHECK-LABEL: define double @trunc_unsigned_f64(
; CHECK-SAME: double [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i64
; CHECK-NEXT: [[I:%.*]] = fptoui double [[X]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i64
; CHECK-NEXT: [[R:%.*]] = uitofp i64 [[I]] to double
; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret double [[R]]
;
%i = fptoui double %x to i64
%r = uitofp i64 %i to double
ret double %r
}
define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: define <4 x float> @trunc_unsigned_v4f32(
; CHECK-SAME: <4 x float> [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>
; CHECK-NEXT: [[I:%.*]] = fptoui <4 x float> [[X]] to <4 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32>
; CHECK-NEXT: [[R:%.*]] = uitofp <4 x i32> [[I]] to <4 x float>
; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret <4 x float> [[R]]
;
%i = fptoui <4 x float> %x to <4 x i32>
%r = uitofp <4 x i32> %i to <4 x float>
ret <4 x float> %r
}
define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
; CHECK-LABEL: define <2 x double> @trunc_unsigned_v2f64(
; CHECK-SAME: <2 x double> [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>
; CHECK-NEXT: [[I:%.*]] = fptoui <2 x double> [[X]] to <2 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i64>
; CHECK-NEXT: [[R:%.*]] = uitofp <2 x i64> [[I]] to <2 x double>
; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret <2 x double> [[R]]
;
%i = fptoui <2 x double> %x to <2 x i64>
%r = uitofp <2 x i64> %i to <2 x double>
ret <2 x double> %r
}
define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
; CHECK-LABEL: define <4 x double> @trunc_unsigned_v4f64(
; CHECK-SAME: <4 x double> [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i64>
; CHECK-NEXT: [[I:%.*]] = fptoui <4 x double> [[X]] to <4 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i64>
; CHECK-NEXT: [[R:%.*]] = uitofp <4 x i64> [[I]] to <4 x double>
; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret <4 x double> [[R]]
;
%i = fptoui <4 x double> %x to <4 x i64>
%r = uitofp <4 x i64> %i to <4 x double>
ret <4 x double> %r
}
define float @trunc_signed_f32_nsz(float %x) #0 {
; CHECK-LABEL: define float @trunc_signed_f32_nsz(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[I:%.*]] = fptosi float [[X]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[R:%.*]] = sitofp i32 [[I]] to float
; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret float [[R]]
;
%i = fptosi float %x to i32
%r = sitofp i32 %i to float
ret float %r
}
define double @trunc_signed32_f64_no_fast_math(double %x) #0 {
; CHECK-LABEL: define double @trunc_signed32_f64_no_fast_math(
; CHECK-SAME: double [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[I:%.*]] = fptosi double [[X]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP5]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP4]] to i64
; CHECK-NEXT: [[R:%.*]] = sitofp i32 [[I]] to double
; CHECK-NEXT: store i64 [[TMP3]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret double [[R]]
;
%i = fptosi double %x to i32
%r = sitofp i32 %i to double
ret double %r
}
define double @trunc_signed32_f64_nsz(double %x) #0 {
; CHECK-LABEL: define double @trunc_signed32_f64_nsz(
; CHECK-SAME: double [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[I:%.*]] = fptosi double [[X]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP5]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP4]] to i64
; CHECK-NEXT: [[R:%.*]] = sitofp i32 [[I]] to double
; CHECK-NEXT: store i64 [[TMP3]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret double [[R]]
;
%i = fptosi double %x to i32
%r = sitofp i32 %i to double
ret double %r
}
define double @trunc_f32_signed32_f64_nsz(float %x) #0 {
; CHECK-LABEL: define double @trunc_f32_signed32_f64_nsz(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP5]] to i32
; CHECK-NEXT: [[I:%.*]] = fptosi float [[X]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP4]] to i64
; CHECK-NEXT: [[R:%.*]] = sitofp i32 [[I]] to double
; CHECK-NEXT: store i64 [[TMP2]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret double [[R]]
;
%i = fptosi float %x to i32
%r = sitofp i32 %i to double
ret double %r
}
define float @trunc_f64_signed32_f32_nsz(double %x) #0 {
; CHECK-LABEL: define float @trunc_f64_signed32_f32_nsz(
; CHECK-SAME: double [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP5]] to i32
; CHECK-NEXT: [[I:%.*]] = fptosi double [[X]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[R:%.*]] = sitofp i32 [[I]] to float
; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret float [[R]]
;
%i = fptosi double %x to i32
%r = sitofp i32 %i to float
ret float %r
}
define double @trunc_signed_f64_nsz(double %x) #0 {
; CHECK-LABEL: define double @trunc_signed_f64_nsz(
; CHECK-SAME: double [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i64
; CHECK-NEXT: [[I:%.*]] = fptosi double [[X]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i64
; CHECK-NEXT: [[R:%.*]] = sitofp i64 [[I]] to double
; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret double [[R]]
;
%i = fptosi double %x to i64
%r = sitofp i64 %i to double
ret double %r
}
define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) #0 {
; CHECK-LABEL: define <4 x float> @trunc_signed_v4f32_nsz(
; CHECK-SAME: <4 x float> [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>
; CHECK-NEXT: [[I:%.*]] = fptosi <4 x float> [[X]] to <4 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32>
; CHECK-NEXT: [[R:%.*]] = sitofp <4 x i32> [[I]] to <4 x float>
; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret <4 x float> [[R]]
;
%i = fptosi <4 x float> %x to <4 x i32>
%r = sitofp <4 x i32> %i to <4 x float>
ret <4 x float> %r
}
define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 {
; CHECK-LABEL: define <2 x double> @trunc_signed_v2f64_nsz(
; CHECK-SAME: <2 x double> [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>
; CHECK-NEXT: [[I:%.*]] = fptosi <2 x double> [[X]] to <2 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i64>
; CHECK-NEXT: [[R:%.*]] = sitofp <2 x i64> [[I]] to <2 x double>
; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret <2 x double> [[R]]
;
%i = fptosi <2 x double> %x to <2 x i64>
%r = sitofp <2 x i64> %i to <2 x double>
ret <2 x double> %r
}
define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
; CHECK-LABEL: define <4 x double> @trunc_signed_v4f64_nsz(
; CHECK-SAME: <4 x double> [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i64>
; CHECK-NEXT: [[I:%.*]] = fptosi <4 x double> [[X]] to <4 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i64>
; CHECK-NEXT: [[R:%.*]] = sitofp <4 x i64> [[I]] to <4 x double>
; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret <4 x double> [[R]]
;
%i = fptosi <4 x double> %x to <4 x i64>
%r = sitofp <4 x i64> %i to <4 x double>
ret <4 x double> %r
}
define float @trunc_unsigned_f32_disable_via_intrinsic(float %x) #0 {
; CHECK-LABEL: define float @trunc_unsigned_f32_disable_via_intrinsic(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[I:%.*]] = call i32 @llvm.fptoui.sat.i32.f32(float [[X]])
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[_MSPROP:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[R:%.*]] = uitofp i32 [[I]] to float
; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret float [[R]]
;
%i = call i32 @llvm.fptoui.sat.i32.f32(float %x)
%r = uitofp i32 %i to float
ret float %r
}
define double @trunc_signed_f64_disable_via_intrinsic(double %x) #0 {
; CHECK-LABEL: define double @trunc_signed_f64_disable_via_intrinsic(
; CHECK-SAME: double [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i64
; CHECK-NEXT: [[I:%.*]] = call i64 @llvm.fptosi.sat.i64.f64(double [[X]])
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
; CHECK-NEXT: [[_MSPROP:%.*]] = sext i1 [[TMP4]] to i64
; CHECK-NEXT: [[R:%.*]] = sitofp i64 [[I]] to double
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret double [[R]]
;
%i = call i64 @llvm.fptosi.sat.i64.f64(double %x)
%r = sitofp i64 %i to double
ret double %r
}
attributes #0 = { sanitize_memory }
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