derek.holloway
7502bf64a4
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95 lines
4.5 KiB
ArmAsm
95 lines
4.5 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-b16b16 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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bfmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: bfmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: bfmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
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// CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid indexed-vector or single-vector register
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bfmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
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// CHECK-NEXT: bfmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w8, 1], {z0.h-z3.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
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// CHECK-NEXT: bfmls za.h[w8, 1], {z0.h-z3.h}, z16.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector select register
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bfmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
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// CHECK-NEXT: bfmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
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// CHECK-NEXT: bfmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector select offset
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bfmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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bfmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h
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// CHECK-NEXT: bfmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector lane index
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bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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