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42 lines
1.6 KiB
ArmAsm
42 lines
1.6 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+sve-b16b16 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector lane index
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bfmls z0.h, z0.h, z0.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls z0.h, z0.h, z0.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls z0.h, z0.h, z0.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmls z0.h, z0.h, z0.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls z0.h, z0.h, z8.h[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
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// CHECK-NEXT: bfmls z0.h, z0.h, z8.h[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector suffix
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bfmls z0.h, z0.s, z0.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfmls z0.h, z0.s, z0.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmls z23.s, z23.h, z13.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfmls z23.s, z23.h, z13.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid use of movprfx
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movprfx z23.h, p1/m, z31.h
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bfmls z23.h, z12.h, z0.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: bfmls z23.h, z12.h, z0.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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