derek.holloway
7502bf64a4
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44 lines
2.2 KiB
ArmAsm
44 lines
2.2 KiB
ArmAsm
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1100 --show-inst < %s | FileCheck %s
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// CHECK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
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buffer_load_dwordx4 v[0:3], v0, s[0:3], 0, offen offset:4092 slc
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// CHECK: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092 slc ; <MCInst #{{[0-9]+}} BUFFER_LOAD_DWORDX4_OFFEN_gfx11
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// CHECK-NEXT: ; <MCOperand Reg:VGPR0_VGPR1_VGPR2_VGPR3>
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// CHECK-NEXT: ; <MCOperand Reg:VGPR0>
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// CHECK-NEXT: ; <MCOperand Reg:SGPR0_SGPR1_SGPR2_SGPR3>
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// CHECK-NEXT: ; <MCOperand Imm:0>
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// CHECK-NEXT: ; <MCOperand Imm:4092>
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// CHECK-NEXT: ; <MCOperand Imm:2>
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// CHECK-NEXT: ; <MCOperand Imm:0>>
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buffer_store_dword v0, v1, s[0:3], 0 offen slc
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// CHECK: buffer_store_b32 v0, v1, s[0:3], 0 offen slc ; <MCInst #{{[0-9]+}} BUFFER_STORE_DWORD_OFFEN_gfx11
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// CHECK-NEXT: ; <MCOperand Reg:VGPR0>
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// CHECK-NEXT: ; <MCOperand Reg:VGPR1>
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// CHECK-NEXT: ; <MCOperand Reg:SGPR0_SGPR1_SGPR2_SGPR3>
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// CHECK-NEXT: ; <MCOperand Imm:0>
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// CHECK-NEXT: ; <MCOperand Imm:0>
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// CHECK-NEXT: ; <MCOperand Imm:2>
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// CHECK-NEXT: ; <MCOperand Imm:0>>
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; tbuffer ops use autogenerate asm parsers
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tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc
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// CHECK: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc ; <MCInst #{{[0-9]+}} TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11
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// CHECK-NEXT: ; <MCOperand Reg:VGPR0_VGPR1_VGPR2_VGPR3>
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// CHECK-NEXT: ; <MCOperand Reg:VGPR0>
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// CHECK-NEXT: ; <MCOperand Reg:SGPR0_SGPR1_SGPR2_SGPR3>
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// CHECK-NEXT: ; <MCOperand Imm:0>
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// CHECK-NEXT: ; <MCOperand Imm:4092>
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// CHECK-NEXT: ; <MCOperand Imm:49>
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// CHECK-NEXT: ; <MCOperand Imm:2>
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// CHECK-NEXT: ; <MCOperand Imm:0>>
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tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc
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// CHECK: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc ; <MCInst #{{[0-9]+}} TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11
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// CHECK-NEXT: ; <MCOperand Reg:VGPR0>
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// CHECK-NEXT: ; <MCOperand Reg:VGPR1>
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// CHECK-NEXT: ; <MCOperand Reg:SGPR0_SGPR1_SGPR2_SGPR3>
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// CHECK-NEXT: ; <MCOperand Imm:0>
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// CHECK-NEXT: ; <MCOperand Imm:0>
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// CHECK-NEXT: ; <MCOperand Imm:33>
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// CHECK-NEXT: ; <MCOperand Imm:2>
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// CHECK-NEXT: ; <MCOperand Imm:0>>
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