derek.holloway
7502bf64a4
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54 lines
1.7 KiB
ArmAsm
54 lines
1.7 KiB
ArmAsm
@ RUN: llvm-mc -triple arm-none-eabi -filetype asm %s 2>%t | FileCheck %s
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@ RUN: FileCheck %s <%t --check-prefix=STDERR
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@ Start in arm mode
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.arm
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@ CHECK: .code 32
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@ In ARM mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in ARM mode)
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.arch armv7-a
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@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:
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@ CHECK-NOT: .code
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@ CHECK: .arch armv7-a
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@ CHECK-NOT: .code
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@ In ARM mode, switch to an arch which has Thumb only, expect warning and .code 16 directive
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.arch armv6-m
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@ STDERR: [[@LINE-1]]:{{[0-9]+}}: warning: new target does not support arm mode, switching to thumb mode
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@ CHECK: .code 16
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@ CHECK: .arch armv6-m
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@ In Thumb mode, switch to an arch which has ARM and Thumb, no warning or .code directive (stay in Thumb mode)
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.arch armv7-a
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@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:
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@ CHECK-NOT: .code
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@ CHECK: .arch armv7-a
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@ CHECK-NOT: .code
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@ In Thumb mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in Thumb mode)
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.cpu cortex-a8
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@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:
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@ CHECK-NOT: .code
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@ CHECK: .cpu cortex-a8
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@ CHECK-NOT: .code
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@ Switch to ARM mode
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.arm
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@ CHECK: .code 32
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@ CHECK: .p2align 2
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@ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM mode)
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.cpu cortex-a8
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@ STDERR-NOT: [[@LINE-1]]:{{[0-9]+}}: warning:
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@ CHECK-NOT: .code
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@ CHECK: .cpu cortex-a8
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@ CHECK-NOT: .code
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@ In ARM mode, switch to a CPU which has Thumb only, expect warning and .code 16 directive
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.cpu cortex-m3
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@ STDERR: [[@LINE-1]]:{{[0-9]+}}: warning: new target does not support arm mode, switching to thumb mode
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@ CHECK: .cpu cortex-m3
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@ CHECK: .code 16
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@ We don't have any ARM-only targets (i.e. v4), so we can't test the forced Thumb->ARM case
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