derek.holloway
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27 lines
1001 B
Plaintext
27 lines
1001 B
Plaintext
# RUN: llvm-mc -triple=xtensa -mattr=+interrupt -disassemble %s | FileCheck -check-prefixes=CHECK-EXCEPTION %s
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# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
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## Verify that binary code is correctly disassembled with
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## Xtensa interrupt option enabled. Also verify that dissasembling without
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## Xtensa interrupt option generates warnings.
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[0x20,0x61,0x00]
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# CHECK-EXCEPTION: rsil a2, 1
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# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
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[0x00,0x71,0x00]
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# CHECK-EXCEPTION: waiti 1
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# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
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[0x20, 0xe4, 0x61]
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#CHECK-INST: xsr a2, intenable
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#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
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[0x20, 0xe2, 0x03]
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#CHECK-INST: rsr a2, interrupt
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#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
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[0x20, 0xe3, 0x13]
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#CHECK-INST: wsr a2, intclear
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#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
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