derek.holloway
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199 lines
7.1 KiB
ArmAsm
199 lines
7.1 KiB
ArmAsm
# The file testing Nop insertion with R_RISCV_ALIGN for relaxation.
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# Relaxation enabled:
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
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# RUN: | llvm-objdump -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=RELAX-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELAX-RELOC %s
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# Relaxation disabled:
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
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# RUN: | llvm-objdump -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=NORELAX-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=NORELAX-RELOC %s
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# Relaxation enabled with C extension:
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
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# RUN: | llvm-objdump -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-RELOC %s
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# Relaxation enabled with Zca extension:
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,+relax < %s \
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# RUN: | llvm-objdump --mattr=+zca -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,+relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-RELOC %s
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# Relaxation disabled with C extension:
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \
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# RUN: | llvm-objdump -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-RELOC %s
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# Relaxation disabled with ZCA extension:
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,-relax < %s \
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# RUN: | llvm-objdump --mattr=+zca -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zca,-relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-RELOC %s
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# We need to insert N-MinNopSize bytes NOPs and R_RISCV_ALIGN relocation
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# type for .align N directive when linker relaxation enabled.
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# Linker could satisfy alignment by removing NOPs after linker relaxation.
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test:
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## Start with a linker-relaxable instruction so that the following alignment can be relaxable.
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call foo
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# NORELAX-RELOC: R_RISCV_CALL_PLT
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# C-OR-ZCA-EXT-NORELAX-RELOC: R_RISCV_CALL_PLT
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.p2align 2
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# If the +c extension is enabled, the text section will be 2-byte aligned, so
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# one c.nop instruction is sufficient.
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# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x2
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# C-OR-ZCA-EXT-RELAX-INST: c.nop
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bne zero, a0, .LBB0_2
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mv a0, zero
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.p2align 3
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# RELAX-RELOC: R_RISCV_ALIGN - 0x6
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# RELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
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# C-OR-ZCA-EXT-RELAX-INST: c.nop
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# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-NORELAX-INST: addi zero, zero, 0
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add a0, a0, a1
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.align 4
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.LBB0_2:
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# RELAX-RELOC: R_RISCV_ALIGN - 0xE
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# RELAX-INST: addi zero, zero, 0
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# RELAX-INST: addi zero, zero, 0
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# RELAX-INST: addi zero, zero, 0
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# NORELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0xE
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# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-RELAX-INST: c.nop
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# C-EXT-INST: addi zero, zero, 0
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# C-EXT-INST: c.nop
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add a0, a0, a1
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.p2align 3
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.constant_pool:
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.long 3126770193
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# RELAX-RELOC: R_RISCV_ALIGN - 0x6
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# RELAX-INST: addi zero, zero, 0
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# NORELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
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# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
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# C-OR-ZCA-EXT-RELAX-INST-NOT: c.nop
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# C-EXT-INST: addi zero, zero, 0
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# C-EXT-INST: c.nop
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add a0, a0, a1
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# Alignment directive with specific padding value 0x01.
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# We will not emit R_RISCV_ALIGN in this case.
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# The behavior is the same as GNU assembler.
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.p2align 4, 1
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# RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xC
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# RELAX-INST: 0101
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# RELAX-INST: 0101
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# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xE
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# C-OR-ZCA-EXT-RELAX-INST: 0101
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# C-EXT-INST: 0101
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ret
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# NORELAX-RELOC-NOT: R_RISCV
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# C-OR-ZCA-EXT-NORELAX-RELOC-NOT: R_RISCV
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# Code alignment of a byte size less than the size of a nop must be treated
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# as no alignment. This used to trigger a fatal error with relaxation enabled
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# as the calculation to emit the worst-case sequence of nops would overflow.
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.p2align 1
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add a0, a0, a1
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.p2align 0
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add a0, a0, a1
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# We only need to insert R_RISCV_ALIGN for code section
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# when the linker relaxation enabled.
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.data
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.p2align 3
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# RELAX-RELOC-NOT: R_RISCV_ALIGN
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# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN
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data1:
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.word 7
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.p2align 4
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# RELAX-RELOC-NOT: R_RISCV_ALIGN
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# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN
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data2:
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.word 9
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# Check that the initial alignment is properly handled when using .option to
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# disable the C extension. This used to crash.
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# C-OR-ZCA-EXT-RELAX-INST: <.text2>:
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# C-OR-ZCA-EXT-RELAX-INST-NEXT: add a0, a0, a1
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.section .text2, "x"
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.option norvc
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.balign 4
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add a0, a0, a1
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## Branches crossing the linker-relaxable R_RISCV_ALIGN need relocations.
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# RELAX-RELOC: .rela.text3 {
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# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6
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# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: }
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# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3 {
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.section .text3, "ax"
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bnez t1, 1f
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bnez t2, 2f
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1:
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.p2align 3
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2:
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bnez t1, 1b
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bnez t1, 2b
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## .text3 with a call at the start
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# NORELAX-RELOC: .rela.text3a
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# RELAX-RELOC: .rela.text3a {
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# RELAX-RELOC-NEXT: 0x0 R_RISCV_CALL_PLT foo 0x0
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# RELAX-RELOC-NEXT: 0x0 R_RISCV_RELAX - 0x0
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# RELAX-RELOC-NEXT: 0x8 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x10 R_RISCV_ALIGN - 0x6
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# RELAX-RELOC-NEXT: 0x16 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x1A R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: }
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# C-OR-ZCA-EXT-NORELAX-RELOC: .rela.text3a
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# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3a
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.section .text3a, "ax"
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call foo
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bnez t1, 1f
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bnez t2, 2f
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1:
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.p2align 3
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2:
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bnez t1, 1b
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bnez t1, 2b
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## .text3 with a call at the end
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# RELAX-RELOC: .rela.text3b {
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# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6
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# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0
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# RELAX-RELOC-NEXT: 0x16 R_RISCV_CALL_PLT foo 0x0
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# RELAX-RELOC-NEXT: 0x16 R_RISCV_RELAX - 0x0
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# RELAX-RELOC-NEXT: }
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.section .text3b, "ax"
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bnez t1, 1f
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bnez t2, 2f
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1:
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.p2align 3
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2:
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bnez t1, 1b
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bnez t1, 2b
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call foo
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