derek.holloway
7502bf64a4
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71 lines
1.7 KiB
ArmAsm
71 lines
1.7 KiB
ArmAsm
# RUN: llvm-mc -triple riscv32 < %s \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
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# RUN: llvm-mc -triple riscv64 < %s \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
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# Check .option relax causes R_RISCV_RELAX to be emitted, and .option
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# norelax suppresses it. Also check that if .option relax was enabled
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# at any point and an instruction may have been relaxed, diff & branch
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# relocations are emitted to ensure correct codegen. See
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# linker-relaxation.s and fixups-expr.s for behaviour of the relax
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# attribute.
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.L1:
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.option norelax
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# CHECK-INST: .option norelax
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# CHECK-INST: call foo
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# CHECK-RELOC: R_RISCV_CALL_PLT foo 0x0
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# CHECK-RELOC-NOT: R_RISCV
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call foo
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.dword .L2-.L1
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jal zero, .L1
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beq s1, s1, .L1
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.L2:
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.option relax
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# CHECK-INST: .option relax
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# CHECK-INST: call bar
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# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT bar 0x0
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# CHECK-RELOC-NEXT: R_RISCV_RELAX - 0x0
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call bar
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.dword .L2-.L1
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# CHECK-RELOC-NEXT: R_RISCV_JAL
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# CHECK-RELOC-NEXT: R_RISCV_RELAX
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jal zero, .L1
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# CHECK-RELOC-NEXT: R_RISCV_BRANCH
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beq s1, s1, .L1
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.option norelax
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# CHECK-INST: .option norelax
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# CHECK-INST: call baz
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# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT baz 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
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call baz
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.dword .L2-.L1
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# CHECK-RELOC-NEXT: R_RISCV_JAL
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jal zero, .L1
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# CHECK-RELOC-NEXT: R_RISCV_BRANCH
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beq s1, s1, .L1
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1:
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# CHECK-RELOC-NEXT: R_RISCV_PCREL_HI20 .L1
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auipc t1, %pcrel_hi(.L1)
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# CHECK-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0
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addi t1, t1, %pcrel_lo(1b)
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# CHECK-RELOC-NOT: .rela.text1
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.section .text1,"ax"
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nop
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call .text1
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