derek.holloway
7502bf64a4
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19 lines
1.1 KiB
ArmAsm
19 lines
1.1 KiB
ArmAsm
# RUN: not llvm-mc -triple riscv32 -mattr=+a,+zacas < %s 2>&1 | FileCheck %s
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# Non-zero offsets not supported for the third operand (rs1).
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amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
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amocas.d a0, a2, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
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# First and second operands (rd and rs2) of amocas.d must be even for RV32.
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amocas.d a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: register must be even
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amocas.d a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: register must be even
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amocas.d.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: register must be even
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amocas.d.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: register must be even
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amocas.d.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: register must be even
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amocas.d.rl a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: register must be even
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amocas.d.aqrl a1, a2, (a1) # CHECK: :[[@LINE]]:15: error: register must be even
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amocas.d.aqrl a0, a1, (a1) # CHECK: :[[@LINE]]:19: error: register must be even
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# amocas.q is not supported for RV32.
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amocas.q a0, a0, (a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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