derek.holloway
7502bf64a4
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248 lines
11 KiB
ArmAsm
248 lines
11 KiB
ArmAsm
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32f %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32f %s \
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# RUN: | llvm-objdump -d --mattr=+zve32f - \
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# RUN: | FileCheck %s --check-prefix=CHECK-INST
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vfmacc.vv v8, v20, v4, v0.t
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# CHECK-INST: vfmacc.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xb0]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmacc.vv v8, v20, v4
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# CHECK-INST: vfmacc.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xb2]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmacc.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfmacc.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xb0]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmacc.vf v8, fa0, v4
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# CHECK-INST: vfmacc.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xb2]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmacc.vv v8, v20, v4, v0.t
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# CHECK-INST: vfnmacc.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xb4]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmacc.vv v8, v20, v4
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# CHECK-INST: vfnmacc.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xb6]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmacc.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfnmacc.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xb4]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmacc.vf v8, fa0, v4
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# CHECK-INST: vfnmacc.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xb6]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsac.vv v8, v20, v4, v0.t
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# CHECK-INST: vfmsac.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xb8]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsac.vv v8, v20, v4
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# CHECK-INST: vfmsac.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xba]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsac.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfmsac.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xb8]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsac.vf v8, fa0, v4
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# CHECK-INST: vfmsac.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xba]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsac.vv v8, v20, v4, v0.t
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# CHECK-INST: vfnmsac.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xbc]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsac.vv v8, v20, v4
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# CHECK-INST: vfnmsac.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xbe]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsac.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfnmsac.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xbc]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsac.vf v8, fa0, v4
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# CHECK-INST: vfnmsac.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xbe]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmadd.vv v8, v20, v4, v0.t
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# CHECK-INST: vfmadd.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xa0]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmadd.vv v8, v20, v4
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# CHECK-INST: vfmadd.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xa2]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmadd.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfmadd.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xa0]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmadd.vf v8, fa0, v4
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# CHECK-INST: vfmadd.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xa2]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmadd.vv v8, v20, v4, v0.t
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# CHECK-INST: vfnmadd.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xa4]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmadd.vv v8, v20, v4
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# CHECK-INST: vfnmadd.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xa6]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmadd.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfnmadd.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xa4]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmadd.vf v8, fa0, v4
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# CHECK-INST: vfnmadd.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xa6]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsub.vv v8, v20, v4, v0.t
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# CHECK-INST: vfmsub.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xa8]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsub.vv v8, v20, v4
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# CHECK-INST: vfmsub.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xaa]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsub.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfmsub.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xa8]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfmsub.vf v8, fa0, v4
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# CHECK-INST: vfmsub.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xaa]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsub.vv v8, v20, v4, v0.t
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# CHECK-INST: vfnmsub.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xac]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsub.vv v8, v20, v4
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# CHECK-INST: vfnmsub.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xae]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsub.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfnmsub.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xac]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfnmsub.vf v8, fa0, v4
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# CHECK-INST: vfnmsub.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xae]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmacc.vv v8, v20, v4, v0.t
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# CHECK-INST: vfwmacc.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xf0]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmacc.vv v8, v20, v4
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# CHECK-INST: vfwmacc.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xf2]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmacc.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfwmacc.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xf0]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmacc.vf v8, fa0, v4
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# CHECK-INST: vfwmacc.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xf2]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmacc.vv v8, v20, v4, v0.t
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# CHECK-INST: vfwnmacc.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xf4]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmacc.vv v8, v20, v4
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# CHECK-INST: vfwnmacc.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xf6]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmacc.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfwnmacc.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xf4]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmacc.vf v8, fa0, v4
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# CHECK-INST: vfwnmacc.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xf6]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmsac.vv v8, v20, v4, v0.t
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# CHECK-INST: vfwmsac.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xf8]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmsac.vv v8, v20, v4
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# CHECK-INST: vfwmsac.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xfa]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmsac.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfwmsac.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xf8]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwmsac.vf v8, fa0, v4
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# CHECK-INST: vfwmsac.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xfa]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmsac.vv v8, v20, v4, v0.t
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# CHECK-INST: vfwnmsac.vv v8, v20, v4, v0.t
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xfc]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmsac.vv v8, v20, v4
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# CHECK-INST: vfwnmsac.vv v8, v20, v4
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# CHECK-ENCODING: [0x57,0x14,0x4a,0xfe]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmsac.vf v8, fa0, v4, v0.t
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# CHECK-INST: vfwnmsac.vf v8, fa0, v4, v0.t
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# CHECK-ENCODING: [0x57,0x54,0x45,0xfc]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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vfwnmsac.vf v8, fa0, v4
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# CHECK-INST: vfwnmsac.vf v8, fa0, v4
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# CHECK-ENCODING: [0x57,0x54,0x45,0xfe]
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# CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}}
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