derek.holloway
7502bf64a4
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155 lines
7.2 KiB
ArmAsm
155 lines
7.2 KiB
ArmAsm
# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v,+xsfvcp %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xsfvcp %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v,+xsfvcp %s \
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# RUN: | llvm-objdump -d --mattr=+v,+xsfvcp --no-print-imm-hex - \
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# RUN: | FileCheck %s --check-prefix=CHECK-INST
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# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvcp %s \
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# RUN: | llvm-objdump -d --mattr=+v,+xsfvcp --no-print-imm-hex - \
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# RUN: | FileCheck %s --check-prefix=CHECK-INST
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sf.vc.x 0x3, 0xf, 0x1f, a1
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# CHECK-INST: sf.vc.x 3, 15, 31, a1
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# CHECK-ENCODING: [0xdb,0xcf,0xf5,0x0e]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.i 0x3, 0xf, 0x1f, 15
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# CHECK-INST: sf.vc.i 3, 15, 31, 15
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# CHECK-ENCODING: [0xdb,0xbf,0xf7,0x0e]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.vv 0x3, 0x1f, v2, v1
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# CHECK-INST: sf.vc.vv 3, 31, v2, v1
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# CHECK-ENCODING: [0xdb,0x8f,0x20,0x2e]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.xv 0x3, 0x1f, v2, a1
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# CHECK-INST: sf.vc.xv 3, 31, v2, a1
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# CHECK-ENCODING: [0xdb,0xcf,0x25,0x2e]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.iv 0x3, 0x1f, v2, 15
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# CHECK-INST: sf.vc.iv 3, 31, v2, 15
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# CHECK-ENCODING: [0xdb,0xbf,0x27,0x2e]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.fv 0x1, 0x1f, v2, fa1
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# CHECK-INST: sf.vc.fv 1, 31, v2, fa1
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# CHECK-ENCODING: [0xdb,0xdf,0x25,0x2e]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.vvv 0x3, v0, v2, v1
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# CHECK-INST: sf.vc.vvv 3, v0, v2, v1
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# CHECK-ENCODING: [0x5b,0x80,0x20,0xae]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.xvv 0x3, v0, v2, a1
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# CHECK-INST: sf.vc.xvv 3, v0, v2, a1
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# CHECK-ENCODING: [0x5b,0xc0,0x25,0xae]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.ivv 0x3, v0, v2, 15
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# CHECK-INST: sf.vc.ivv 3, v0, v2, 15
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# CHECK-ENCODING: [0x5b,0xb0,0x27,0xae]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.fvv 0x1, v0, v2, fa1
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# CHECK-INST: sf.vc.fvv 1, v0, v2, fa1
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# CHECK-ENCODING: [0x5b,0xd0,0x25,0xae]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.vvw 0x3, v0, v2, v1
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# CHECK-INST: sf.vc.vvw 3, v0, v2, v1
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# CHECK-ENCODING: [0x5b,0x80,0x20,0xfe]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.xvw 0x3, v0, v2, a1
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# CHECK-INST: sf.vc.xvw 3, v0, v2, a1
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# CHECK-ENCODING: [0x5b,0xc0,0x25,0xfe]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.ivw 0x3, v0, v2, 15
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# CHECK-INST: sf.vc.ivw 3, v0, v2, 15
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# CHECK-ENCODING: [0x5b,0xb0,0x27,0xfe]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.fvw 0x1, v0, v2, fa1
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# CHECK-INST: sf.vc.fvw 1, v0, v2, fa1
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# CHECK-ENCODING: [0x5b,0xd0,0x25,0xfe]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.x 0x3, 0xf, v0, a1
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# CHECK-INST: sf.vc.v.x 3, 15, v0, a1
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# CHECK-ENCODING: [0x5b,0xc0,0xf5,0x0c]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.i 0x3, 0xf, v0, 15
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# CHECK-INST: sf.vc.v.i 3, 15, v0, 15
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# CHECK-ENCODING: [0x5b,0xb0,0xf7,0x0c]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.vv 0x3, v0, v2, v1
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# CHECK-INST: sf.vc.v.vv 3, v0, v2, v1
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# CHECK-ENCODING: [0x5b,0x80,0x20,0x2c]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.xv 0x3, v0, v2, a1
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# CHECK-INST: sf.vc.v.xv 3, v0, v2, a1
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# CHECK-ENCODING: [0x5b,0xc0,0x25,0x2c]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.iv 0x3, v0, v2, 15
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# CHECK-INST: sf.vc.v.iv 3, v0, v2, 15
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# CHECK-ENCODING: [0x5b,0xb0,0x27,0x2c]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.fv 0x1, v0, v2, fa1
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# CHECK-INST: sf.vc.v.fv 1, v0, v2, fa1
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# CHECK-ENCODING: [0x5b,0xd0,0x25,0x2c]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.vvv 0x3, v0, v2, v1
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# CHECK-INST: sf.vc.v.vvv 3, v0, v2, v1
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# CHECK-ENCODING: [0x5b,0x80,0x20,0xac]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.xvv 0x3, v0, v2, a1
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# CHECK-INST: sf.vc.v.xvv 3, v0, v2, a1
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# CHECK-ENCODING: [0x5b,0xc0,0x25,0xac]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.ivv 0x3, v0, v2, 15
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# CHECK-INST: sf.vc.v.ivv 3, v0, v2, 15
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# CHECK-ENCODING: [0x5b,0xb0,0x27,0xac]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.fvv 0x1, v0, v2, fa1
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# CHECK-INST: sf.vc.v.fvv 1, v0, v2, fa1
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# CHECK-ENCODING: [0x5b,0xd0,0x25,0xac]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.vvw 0x3, v0, v2, v1
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# CHECK-INST: sf.vc.v.vvw 3, v0, v2, v1
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# CHECK-ENCODING: [0x5b,0x80,0x20,0xfc]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.xvw 0x3, v0, v2, a1
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# CHECK-INST: sf.vc.v.xvw 3, v0, v2, a1
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# CHECK-ENCODING: [0x5b,0xc0,0x25,0xfc]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.ivw 0x3, v0, v2, 15
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# CHECK-INST: sf.vc.v.ivw 3, v0, v2, 15
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# CHECK-ENCODING: [0x5b,0xb0,0x27,0xfc]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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sf.vc.v.fvw 0x1, v0, v2, fa1
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# CHECK-INST: sf.vc.v.fvw 1, v0, v2, fa1
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# CHECK-ENCODING: [0x5b,0xd0,0x25,0xfc]
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# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}}
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