derek.holloway
7502bf64a4
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2574 lines
137 KiB
ArmAsm
2574 lines
137 KiB
ArmAsm
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v %s \
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# RUN: --M no-aliases \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v %s \
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# RUN: | llvm-objdump -d --mattr=+v -M no-aliases - \
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# RUN: | FileCheck %s --check-prefix=CHECK-INST
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vlseg2e8.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e8.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e8.v v8, (a0)
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# CHECK-INST: vlseg2e8.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x04,0x05,0x22]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e16.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e16.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x54,0x05,0x20]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e16.v v8, (a0)
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# CHECK-INST: vlseg2e16.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x54,0x05,0x22]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e32.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e32.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x64,0x05,0x20]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e32.v v8, (a0)
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# CHECK-INST: vlseg2e32.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x64,0x05,0x22]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e64.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e64.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x74,0x05,0x20]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e64.v v8, (a0)
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# CHECK-INST: vlseg2e64.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x74,0x05,0x22]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e8ff.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e8ff.v v8, (a0)
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# CHECK-INST: vlseg2e8ff.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e16ff.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e16ff.v v8, (a0)
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# CHECK-INST: vlseg2e16ff.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e32ff.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e32ff.v v8, (a0)
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# CHECK-INST: vlseg2e32ff.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e64ff.v v8, (a0), v0.t
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# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e64ff.v v8, (a0)
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# CHECK-INST: vlseg2e64ff.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e8.v v8, (a0), a1, v0.t
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# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t
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# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e8.v v8, (a0), a1
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# CHECK-INST: vlsseg2e8.v v8, (a0), a1
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# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e16.v v8, (a0), a1, v0.t
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# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t
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# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e16.v v8, (a0), a1
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# CHECK-INST: vlsseg2e16.v v8, (a0), a1
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# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e32.v v8, (a0), a1, v0.t
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# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t
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# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e32.v v8, (a0), a1
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# CHECK-INST: vlsseg2e32.v v8, (a0), a1
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# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e64.v v8, (a0), a1, v0.t
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# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t
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# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e64.v v8, (a0), a1
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# CHECK-INST: vlsseg2e64.v v8, (a0), a1
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# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei8.v v8, (a0), v4, v0.t
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# CHECK-INST: vluxseg2ei8.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x04,0x45,0x24]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei8.v v8, (a0), v4
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# CHECK-INST: vluxseg2ei8.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x04,0x45,0x26]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei16.v v8, (a0), v4, v0.t
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# CHECK-INST: vluxseg2ei16.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x54,0x45,0x24]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei16.v v8, (a0), v4
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# CHECK-INST: vluxseg2ei16.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x54,0x45,0x26]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei32.v v8, (a0), v4, v0.t
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# CHECK-INST: vluxseg2ei32.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x64,0x45,0x24]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei32.v v8, (a0), v4
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# CHECK-INST: vluxseg2ei32.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x64,0x45,0x26]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei64.v v8, (a0), v4, v0.t
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# CHECK-INST: vluxseg2ei64.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x74,0x45,0x24]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg2ei64.v v8, (a0), v4
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# CHECK-INST: vluxseg2ei64.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x74,0x45,0x26]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei8.v v8, (a0), v4, v0.t
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# CHECK-INST: vloxseg2ei8.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei8.v v8, (a0), v4
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# CHECK-INST: vloxseg2ei8.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei16.v v8, (a0), v4, v0.t
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# CHECK-INST: vloxseg2ei16.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei16.v v8, (a0), v4
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# CHECK-INST: vloxseg2ei16.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei32.v v8, (a0), v4, v0.t
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# CHECK-INST: vloxseg2ei32.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei32.v v8, (a0), v4
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# CHECK-INST: vloxseg2ei32.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei64.v v8, (a0), v4, v0.t
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# CHECK-INST: vloxseg2ei64.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg2ei64.v v8, (a0), v4
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# CHECK-INST: vloxseg2ei64.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vlseg3e8.v v8, (a0), v0.t
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# CHECK-INST: vlseg3e8.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
|
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg3e8.v v8, (a0)
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# CHECK-INST: vlseg3e8.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg3e16.v v8, (a0), v0.t
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# CHECK-INST: vlseg3e16.v v8, (a0), v0.t
|
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# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg3e16.v v8, (a0)
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# CHECK-INST: vlseg3e16.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg3e32.v v8, (a0), v0.t
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# CHECK-INST: vlseg3e32.v v8, (a0), v0.t
|
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# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg3e32.v v8, (a0)
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# CHECK-INST: vlseg3e32.v v8, (a0)
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|
# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
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|
|
vlseg3e64.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg3e64.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
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|
vlseg3e64.v v8, (a0)
|
|
# CHECK-INST: vlseg3e64.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg3e8ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg3e8ff.v v8, (a0)
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# CHECK-INST: vlseg3e8ff.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg3e16ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg3e16ff.v v8, (a0)
|
|
# CHECK-INST: vlseg3e16ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg3e32ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg3e32ff.v v8, (a0)
|
|
# CHECK-INST: vlseg3e32ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg3e64ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg3e64ff.v v8, (a0)
|
|
# CHECK-INST: vlseg3e64ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e8.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e8.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg3e8.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e16.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e16.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg3e16.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e32.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e32.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg3e32.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e64.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg3e64.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg3e64.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg3ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei8.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg3ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg3ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei16.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg3ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg3ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei32.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg3ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg3ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg3ei64.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg3ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg3ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei8.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg3ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg3ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei16.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg3ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg3ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei32.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg3ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg3ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg3ei64.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg3ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e8.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e8.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e8.v v8, (a0)
|
|
# CHECK-INST: vlseg4e8.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e16.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e16.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e16.v v8, (a0)
|
|
# CHECK-INST: vlseg4e16.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e32.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e32.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e32.v v8, (a0)
|
|
# CHECK-INST: vlseg4e32.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e64.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e64.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e64.v v8, (a0)
|
|
# CHECK-INST: vlseg4e64.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e8ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e8ff.v v8, (a0)
|
|
# CHECK-INST: vlseg4e8ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e16ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e16ff.v v8, (a0)
|
|
# CHECK-INST: vlseg4e16ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e32ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e32ff.v v8, (a0)
|
|
# CHECK-INST: vlseg4e32ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e64ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg4e64ff.v v8, (a0)
|
|
# CHECK-INST: vlseg4e64ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e8.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e8.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg4e8.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e16.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e16.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg4e16.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e32.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e32.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg4e32.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e64.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg4e64.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg4e64.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg4ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei8.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg4ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg4ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei16.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg4ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg4ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei32.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg4ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg4ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg4ei64.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg4ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg4ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei8.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg4ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg4ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei16.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg4ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg4ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei32.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg4ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg4ei64.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg4ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e8.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e8.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e8.v v8, (a0)
|
|
# CHECK-INST: vlseg5e8.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e16.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e16.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e16.v v8, (a0)
|
|
# CHECK-INST: vlseg5e16.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e32.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e32.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e32.v v8, (a0)
|
|
# CHECK-INST: vlseg5e32.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e64.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e64.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e64.v v8, (a0)
|
|
# CHECK-INST: vlseg5e64.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e8ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e8ff.v v8, (a0)
|
|
# CHECK-INST: vlseg5e8ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0x83]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e16ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e16ff.v v8, (a0)
|
|
# CHECK-INST: vlseg5e16ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0x83]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e32ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e32ff.v v8, (a0)
|
|
# CHECK-INST: vlseg5e32ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0x83]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e64ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg5e64ff.v v8, (a0)
|
|
# CHECK-INST: vlseg5e64ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0x83]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e8.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e8.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg5e8.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e16.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e16.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg5e16.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e32.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e32.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg5e32.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e64.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg5e64.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg5e64.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg5ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei8.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg5ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg5ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei16.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg5ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg5ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei32.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg5ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg5ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg5ei64.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg5ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg5ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei8.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg5ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg5ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei16.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg5ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg5ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei32.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg5ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg5ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg5ei64.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg5ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e8.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e8.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e8.v v8, (a0)
|
|
# CHECK-INST: vlseg6e8.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e16.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e16.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e16.v v8, (a0)
|
|
# CHECK-INST: vlseg6e16.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e32.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e32.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e32.v v8, (a0)
|
|
# CHECK-INST: vlseg6e32.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e64.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e64.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e64.v v8, (a0)
|
|
# CHECK-INST: vlseg6e64.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e8ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e8ff.v v8, (a0)
|
|
# CHECK-INST: vlseg6e8ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xa3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e16ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e16ff.v v8, (a0)
|
|
# CHECK-INST: vlseg6e16ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xa3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e32ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e32ff.v v8, (a0)
|
|
# CHECK-INST: vlseg6e32ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xa3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e64ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg6e64ff.v v8, (a0)
|
|
# CHECK-INST: vlseg6e64ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xa3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e8.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e8.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg6e8.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e16.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e16.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg6e16.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e32.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e32.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg6e32.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e64.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg6e64.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg6e64.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg6ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei8.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg6ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg6ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei16.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg6ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg6ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei32.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg6ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg6ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg6ei64.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg6ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg6ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei8.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg6ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg6ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei16.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg6ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg6ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei32.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg6ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg6ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg6ei64.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg6ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e8.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e8.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e8.v v8, (a0)
|
|
# CHECK-INST: vlseg7e8.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e16.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e16.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e16.v v8, (a0)
|
|
# CHECK-INST: vlseg7e16.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e32.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e32.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e32.v v8, (a0)
|
|
# CHECK-INST: vlseg7e32.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e64.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e64.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e64.v v8, (a0)
|
|
# CHECK-INST: vlseg7e64.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e8ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xc1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e8ff.v v8, (a0)
|
|
# CHECK-INST: vlseg7e8ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e16ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xc1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e16ff.v v8, (a0)
|
|
# CHECK-INST: vlseg7e16ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e32ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xc1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e32ff.v v8, (a0)
|
|
# CHECK-INST: vlseg7e32ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e64ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xc1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg7e64ff.v v8, (a0)
|
|
# CHECK-INST: vlseg7e64ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e8.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e8.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg7e8.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e16.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e16.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg7e16.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e32.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e32.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg7e32.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e64.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg7e64.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg7e64.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg7ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei8.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg7ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg7ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei16.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg7ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg7ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei32.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg7ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg7ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg7ei64.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg7ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg7ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei8.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg7ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg7ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei16.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg7ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg7ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei32.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg7ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg7ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg7ei64.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg7ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e8.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e8.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e8.v v8, (a0)
|
|
# CHECK-INST: vlseg8e8.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e16.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e16.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e16.v v8, (a0)
|
|
# CHECK-INST: vlseg8e16.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e32.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e32.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e32.v v8, (a0)
|
|
# CHECK-INST: vlseg8e32.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e64.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e64.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e64.v v8, (a0)
|
|
# CHECK-INST: vlseg8e64.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e8ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e8ff.v v8, (a0)
|
|
# CHECK-INST: vlseg8e8ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x04,0x05,0xe3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e16ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e16ff.v v8, (a0)
|
|
# CHECK-INST: vlseg8e16ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x54,0x05,0xe3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e32ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e32ff.v v8, (a0)
|
|
# CHECK-INST: vlseg8e32ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x64,0x05,0xe3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e64ff.v v8, (a0), v0.t
|
|
# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlseg8e64ff.v v8, (a0)
|
|
# CHECK-INST: vlseg8e64ff.v v8, (a0)
|
|
# CHECK-ENCODING: [0x07,0x74,0x05,0xe3]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e8.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e8.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg8e8.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e16.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e16.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg8e16.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e32.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e32.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg8e32.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e64.v v8, (a0), a1, v0.t
|
|
# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vlsseg8e64.v v8, (a0), a1
|
|
# CHECK-INST: vlsseg8e64.v v8, (a0), a1
|
|
# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg8ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei8.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg8ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg8ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei16.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg8ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg8ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei32.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg8ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vluxseg8ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vluxseg8ei64.v v8, (a0), v4
|
|
# CHECK-INST: vluxseg8ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg8ei8.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei8.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg8ei8.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg8ei16.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei16.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg8ei16.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg8ei32.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei32.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg8ei32.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-INST: vloxseg8ei64.v v8, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vloxseg8ei64.v v8, (a0), v4
|
|
# CHECK-INST: vloxseg8ei64.v v8, (a0), v4
|
|
# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e8.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg2e8.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x20]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e8.v v24, (a0)
|
|
# CHECK-INST: vsseg2e8.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x22]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e16.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg2e16.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x20]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e16.v v24, (a0)
|
|
# CHECK-INST: vsseg2e16.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x22]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e32.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg2e32.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x20]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e32.v v24, (a0)
|
|
# CHECK-INST: vsseg2e32.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x22]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e64.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg2e64.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x20]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg2e64.v v24, (a0)
|
|
# CHECK-INST: vsseg2e64.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x22]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e8.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e8.v v24, (a0), a1
|
|
# CHECK-INST: vssseg2e8.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e16.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x28]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e16.v v24, (a0), a1
|
|
# CHECK-INST: vssseg2e16.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e32.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x28]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e32.v v24, (a0), a1
|
|
# CHECK-INST: vssseg2e32.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e64.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x28]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg2e64.v v24, (a0), a1
|
|
# CHECK-INST: vssseg2e64.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x24]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x26]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x24]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x26]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x24]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x26]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x24]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg2ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x26]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg2ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e8.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg3e8.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x40]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e8.v v24, (a0)
|
|
# CHECK-INST: vsseg3e8.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x42]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e16.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg3e16.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x40]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e16.v v24, (a0)
|
|
# CHECK-INST: vsseg3e16.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x42]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e32.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg3e32.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x40]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e32.v v24, (a0)
|
|
# CHECK-INST: vsseg3e32.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x42]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e64.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg3e64.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x40]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg3e64.v v24, (a0)
|
|
# CHECK-INST: vsseg3e64.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x42]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e8.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e8.v v24, (a0), a1
|
|
# CHECK-INST: vssseg3e8.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e16.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e16.v v24, (a0), a1
|
|
# CHECK-INST: vssseg3e16.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e32.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e32.v v24, (a0), a1
|
|
# CHECK-INST: vssseg3e32.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e64.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x48]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg3e64.v v24, (a0), a1
|
|
# CHECK-INST: vssseg3e64.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x44]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg3ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x46]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg3ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e8.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg4e8.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e8.v v24, (a0)
|
|
# CHECK-INST: vsseg4e8.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e16.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg4e16.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e16.v v24, (a0)
|
|
# CHECK-INST: vsseg4e16.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e32.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg4e32.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e32.v v24, (a0)
|
|
# CHECK-INST: vsseg4e32.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e64.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg4e64.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x60]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg4e64.v v24, (a0)
|
|
# CHECK-INST: vsseg4e64.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x62]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e8.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e8.v v24, (a0), a1
|
|
# CHECK-INST: vssseg4e8.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e16.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e16.v v24, (a0), a1
|
|
# CHECK-INST: vssseg4e16.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e32.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e32.v v24, (a0), a1
|
|
# CHECK-INST: vssseg4e32.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e64.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x68]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg4e64.v v24, (a0), a1
|
|
# CHECK-INST: vssseg4e64.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x64]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg4ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x66]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg4ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e8.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg5e8.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e8.v v24, (a0)
|
|
# CHECK-INST: vsseg5e8.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e16.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg5e16.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e16.v v24, (a0)
|
|
# CHECK-INST: vsseg5e16.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e32.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e32.v v24, (a0)
|
|
# CHECK-INST: vsseg5e32.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e64.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg5e64.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x80]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg5e64.v v24, (a0)
|
|
# CHECK-INST: vsseg5e64.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0x82]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg5e8.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg5e8.v v24, (a0), a1
|
|
# CHECK-INST: vssseg5e8.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg5e16.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg5e16.v v24, (a0), a1
|
|
# CHECK-INST: vssseg5e16.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg5e32.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg5e32.v v24, (a0), a1
|
|
# CHECK-INST: vssseg5e32.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
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vssseg5e64.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x88]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg5e64.v v24, (a0), a1
|
|
# CHECK-INST: vssseg5e64.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x84]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg5ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x86]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg5ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e8.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg6e8.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e8.v v24, (a0)
|
|
# CHECK-INST: vsseg6e8.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e16.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg6e16.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e16.v v24, (a0)
|
|
# CHECK-INST: vsseg6e16.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e32.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg6e32.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e32.v v24, (a0)
|
|
# CHECK-INST: vsseg6e32.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e64.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg6e64.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg6e64.v v24, (a0)
|
|
# CHECK-INST: vsseg6e64.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e8.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e8.v v24, (a0), a1
|
|
# CHECK-INST: vssseg6e8.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e16.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e16.v v24, (a0), a1
|
|
# CHECK-INST: vssseg6e16.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e32.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e32.v v24, (a0), a1
|
|
# CHECK-INST: vssseg6e32.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e64.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg6e64.v v24, (a0), a1
|
|
# CHECK-INST: vssseg6e64.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xa4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg6ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xa6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xac]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg6ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xae]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e8.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg7e8.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e8.v v24, (a0)
|
|
# CHECK-INST: vsseg7e8.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e16.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg7e16.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e16.v v24, (a0)
|
|
# CHECK-INST: vsseg7e16.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e32.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg7e32.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e32.v v24, (a0)
|
|
# CHECK-INST: vsseg7e32.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e64.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg7e64.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg7e64.v v24, (a0)
|
|
# CHECK-INST: vsseg7e64.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e8.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e8.v v24, (a0), a1
|
|
# CHECK-INST: vssseg7e8.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e16.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e16.v v24, (a0), a1
|
|
# CHECK-INST: vssseg7e16.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e32.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e32.v v24, (a0), a1
|
|
# CHECK-INST: vssseg7e32.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e64.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg7e64.v v24, (a0), a1
|
|
# CHECK-INST: vssseg7e64.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xca]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xc4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg7ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xc6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg7ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xce]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e8.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg8e8.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e8.v v24, (a0)
|
|
# CHECK-INST: vsseg8e8.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e16.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg8e16.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e16.v v24, (a0)
|
|
# CHECK-INST: vsseg8e16.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e32.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg8e32.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e32.v v24, (a0)
|
|
# CHECK-INST: vsseg8e32.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e64.v v24, (a0), v0.t
|
|
# CHECK-INST: vsseg8e64.v v24, (a0), v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsseg8e64.v v24, (a0)
|
|
# CHECK-INST: vsseg8e64.v v24, (a0)
|
|
# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e8.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e8.v v24, (a0), a1
|
|
# CHECK-INST: vssseg8e8.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e16.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e16.v v24, (a0), a1
|
|
# CHECK-INST: vssseg8e16.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e32.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e32.v v24, (a0), a1
|
|
# CHECK-INST: vssseg8e32.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e64.v v24, (a0), a1, v0.t
|
|
# CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vssseg8e64.v v24, (a0), a1
|
|
# CHECK-INST: vssseg8e64.v v24, (a0), a1
|
|
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xe4]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsuxseg8ei64.v v24, (a0), v4
|
|
# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x7c,0x45,0xe6]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg8ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xec]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg8ei8.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x0c,0x45,0xee]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg8ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xec]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg8ei16.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x5c,0x45,0xee]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg8ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4, v0.t
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xec]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg8ei32.v v24, (a0), v4
|
|
# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4
|
|
# CHECK-ENCODING: [0x27,0x6c,0x45,0xee]
|
|
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|
|
|
|
vsoxseg8ei64.v v24, (a0), v4, v0.t
|
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# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4, v0.t
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# CHECK-ENCODING: [0x27,0x7c,0x45,0xec]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vsoxseg8ei64.v v24, (a0), v4
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# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4
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# CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e8.v v8, 0(a0), v0.t
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# CHECK-INST: vlseg2e8.v v8, (a0), v0.t
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# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlseg2e16ff.v v8, 0(a0)
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# CHECK-INST: vlseg2e16ff.v v8, (a0)
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# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vlsseg2e8.v v8, 0(a0), a1
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# CHECK-INST: vlsseg2e8.v v8, (a0), a1
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# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vluxseg3ei16.v v8, 0(a0), v4
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# CHECK-INST: vluxseg3ei16.v v8, (a0), v4
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# CHECK-ENCODING: [0x07,0x54,0x45,0x46]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vloxseg4ei64.v v8, 0(a0), v4, v0.t
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# CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t
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# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
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vsseg5e32.v v24, 0(a0), v0.t
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# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
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# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vssseg2e8.v v24, 0(a0), a1, v0.t
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# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
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# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vsoxseg7ei16.v v24, 0(a0), v4
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# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4
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# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
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vsuxseg6ei32.v v24, 0(a0), v4, v0.t
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# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t
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# CHECK-ENCODING: [0x27,0x6c,0x45,0xa4]
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# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
|