derek.holloway
7502bf64a4
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143 lines
4.6 KiB
ArmAsm
143 lines
4.6 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfinx -M no-aliases \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfinx \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx -M no-aliases \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfinx %s \
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# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx -M no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfinx %s \
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# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx - \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfinx %s \
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# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx -M no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfinx %s \
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# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx - \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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##===----------------------------------------------------------------------===##
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## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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##===----------------------------------------------------------------------===##
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# CHECK-INST: fsgnj.s s1, s2, s2
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# CHECK-ALIAS: fmv.s s1, s2
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fmv.s s1, s2
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# CHECK-INST: fsgnjx.s s1, s2, s2
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# CHECK-ALIAS: fabs.s s1, s2
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fabs.s s1, s2
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# CHECK-INST: fsgnjn.s s2, s3, s3
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# CHECK-ALIAS: fneg.s s2, s3
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fneg.s s2, s3
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# CHECK-INST: flt.s tp, s6, s5
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# CHECK-ALIAS: flt.s tp, s6, s5
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fgt.s x4, s5, s6
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# CHECK-INST: fle.s t2, s1, s0
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# CHECK-ALIAS: fle.s t2, s1, s0
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fge.s x7, x8, x9
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# The following instructions actually alias instructions from the base ISA.
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# However, it only makes sense to support them when the F or Zfinx extension is
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# enabled.
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# CHECK-INST: csrrs t0, fcsr, zero
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# CHECK-ALIAS: frcsr t0
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frcsr x5
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# CHECK-INST: csrrw t1, fcsr, t2
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# CHECK-ALIAS: fscsr t1, t2
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fscsr x6, x7
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# CHECK-INST: csrrw zero, fcsr, t3
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# CHECK-ALIAS: fscsr t3
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fscsr x28
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# These are obsolete aliases of frcsr/fscsr. They are accepted by the assembler
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# but the disassembler should always print them as the equivalent, new aliases.
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# CHECK-INST: csrrs t4, fcsr, zero
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# CHECK-ALIAS: frcsr t4
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frsr x29
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# CHECK-INST: csrrw t5, fcsr, t6
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# CHECK-ALIAS: fscsr t5, t6
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fssr x30, x31
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# CHECK-INST: csrrw zero, fcsr, s0
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# CHECK-ALIAS: fscsr s0
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fssr x8
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# CHECK-INST: csrrs t4, frm, zero
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# CHECK-ALIAS: frrm t4
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frrm x29
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# CHECK-INST: csrrw t5, frm, t4
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# CHECK-ALIAS: fsrm t5, t4
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fsrm x30, x29
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# CHECK-INST: csrrw zero, frm, t6
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# CHECK-ALIAS: fsrm t6
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fsrm x31
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# CHECK-INST: csrrwi a0, frm, 31
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# CHECK-ALIAS: fsrmi a0, 31
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fsrmi x10, 0x1f
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# CHECK-INST: csrrwi zero, frm, 30
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# CHECK-ALIAS: fsrmi 30
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fsrmi 0x1e
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# CHECK-INST: csrrs a1, fflags, zero
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# CHECK-ALIAS: frflags a1
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frflags x11
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# CHECK-INST: csrrw a2, fflags, a1
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# CHECK-ALIAS: fsflags a2, a1
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fsflags x12, x11
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# CHECK-INST: csrrw zero, fflags, a3
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# CHECK-ALIAS: fsflags a3
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fsflags x13
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# CHECK-INST: csrrwi a4, fflags, 29
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# CHECK-ALIAS: fsflagsi a4, 29
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fsflagsi x14, 0x1d
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# CHECK-INST: csrrwi zero, fflags, 28
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# CHECK-ALIAS: fsflagsi 28
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fsflagsi 0x1c
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##===----------------------------------------------------------------------===##
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## Aliases which omit the rounding mode.
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##===----------------------------------------------------------------------===##
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# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn
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# CHECK-ALIAS: fmadd.s a0, a1, a2, a3
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fmadd.s x10, x11, x12, x13
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# CHECK-INST: fmsub.s a4, a5, a6, a7, dyn
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# CHECK-ALIAS: fmsub.s a4, a5, a6, a7
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fmsub.s x14, x15, x16, x17
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# CHECK-INST: fnmsub.s s2, s3, s4, s5, dyn
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# CHECK-ALIAS: fnmsub.s s2, s3, s4, s5
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fnmsub.s x18, x19, x20, x21
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# CHECK-INST: fnmadd.s s6, s7, s8, s9, dyn
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# CHECK-ALIAS: fnmadd.s s6, s7, s8, s9
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fnmadd.s x22, x23, x24, x25
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# CHECK-INST: fadd.s s10, s11, t3, dyn
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# CHECK-ALIAS: fadd.s s10, s11, t3
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fadd.s x26, x27, x28
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# CHECK-INST: fsub.s t4, t5, t6, dyn
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# CHECK-ALIAS: fsub.s t4, t5, t6
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fsub.s x29, x30, x31
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# CHECK-INST: fmul.s s0, s1, s2, dyn
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# CHECK-ALIAS: fmul.s s0, s1, s2
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fmul.s s0, s1, s2
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# CHECK-INST: fdiv.s s3, s4, s5, dyn
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# CHECK-ALIAS: fdiv.s s3, s4, s5
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fdiv.s s3, s4, s5
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# CHECK-INST: sqrt.s s6, s7, dyn
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# CHECK-ALIAS: sqrt.s s6, s7
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fsqrt.s s6, s7
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# CHECK-INST: fcvt.w.s a0, s5, dyn
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# CHECK-ALIAS: fcvt.w.s a0, s5
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fcvt.w.s a0, s5
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# CHECK-INST: fcvt.wu.s a1, s6, dyn
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# CHECK-ALIAS: fcvt.wu.s a1, s6
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fcvt.wu.s a1, s6
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# CHECK-INST: fcvt.s.w t6, a4, dyn
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# CHECK-ALIAS: fcvt.s.w t6, a4
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fcvt.s.w t6, a4
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# CHECK-INST: fcvt.s.wu s0, a5, dyn
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# CHECK-ALIAS: fcvt.s.wu s0, a5
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fcvt.s.wu s0, a5
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