derek.holloway
7502bf64a4
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503 lines
12 KiB
ArmAsm
503 lines
12 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-objdump -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
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#
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# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
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# RUN: | llvm-objdump -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
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##################################
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# Supervisor Trap Setup
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##################################
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# sstatus
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# name
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# CHECK-INST: csrrs t1, sstatus, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0x10]
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# CHECK-INST-ALIAS: csrr t1, sstatus
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# uimm12
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# CHECK-INST: csrrs t2, sstatus, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x10]
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# CHECK-INST-ALIAS: csrr t2, sstatus
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# name
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csrrs t1, sstatus, zero
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# uimm12
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csrrs t2, 0x100, zero
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# sie
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# name
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# CHECK-INST: csrrs t1, sie, zero
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# CHECK-ENC: [0x73,0x23,0x40,0x10]
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# CHECK-INST-ALIAS: csrr t1, sie
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# uimm12
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# CHECK-INST: csrrs t2, sie, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x10]
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# CHECK-INST-ALIAS: csrr t2, sie
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# name
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csrrs t1, sie, zero
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# uimm12
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csrrs t2, 0x104, zero
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# stvec
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# name
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# CHECK-INST: csrrs t1, stvec, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x50,0x10]
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# CHECK-INST-ALIAS: csrr t1, stvec
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# uimm12
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# CHECK-INST: csrrs t2, stvec, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x10]
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# CHECK-INST-ALIAS: csrr t2, stvec
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# name
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csrrs t1, stvec, zero
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# uimm12
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csrrs t2, 0x105, zero
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# scounteren
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# name
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# CHECK-INST: csrrs t1, scounteren, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x60,0x10]
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# CHECK-INST-ALIAS: csrr t1, scounteren
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# uimm12
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# CHECK-INST: csrrs t2, scounteren, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x10]
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# CHECK-INST-ALIAS: csrr t2, scounteren
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# name
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csrrs t1, scounteren, zero
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# uimm12
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csrrs t2, 0x106, zero
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# stimecmp
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# name
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# CHECK-INST: csrrs t1, stimecmp, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x14]
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# CHECK-INST-ALIAS: csrr t1, stimecmp
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# uimm12
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# CHECK-INST: csrrs t2, stimecmp, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x14]
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# CHECK-INST-ALIAS: csrr t2, stimecmp
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# name
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csrrs t1, stimecmp, zero
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# uimm12
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csrrs t2, 0x14D, zero
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##################################
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# Supervisor Configuration
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##################################
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# senvcfg
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# name
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# CHECK-INST: csrrs t1, senvcfg, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x10]
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# CHECK-INST-ALIAS: csrr t1, senvcfg
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# uimm12
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# CHECK-INST: csrrs t2, senvcfg, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x10]
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# CHECK-INST-ALIAS: csrr t2, senvcfg
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# name
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csrrs t1, senvcfg, zero
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# uimm12
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csrrs t2, 0x10A, zero
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##################################
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# Supervisor Trap Handling
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##################################
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# sscratch
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# name
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# CHECK-INST: csrrs t1, sscratch, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0x14]
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# CHECK-INST-ALIAS: csrr t1, sscratch
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# uimm12
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# CHECK-INST: csrrs t2, sscratch, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x14]
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# CHECK-INST-ALIAS: csrr t2, sscratch
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# name
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csrrs t1, sscratch, zero
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# uimm12
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csrrs t2, 0x140, zero
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# sepc
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# name
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# CHECK-INST: csrrs t1, sepc, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0x14]
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# CHECK-INST-ALIAS: csrr t1, sepc
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# uimm12
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# CHECK-INST: csrrs t2, sepc, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x14]
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# CHECK-INST-ALIAS: csrr t2, sepc
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# name
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csrrs t1, sepc, zero
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# uimm12
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csrrs t2, 0x141, zero
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# scause
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# name
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# CHECK-INST: csrrs t1, scause, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x20,0x14]
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# CHECK-INST-ALIAS: csrr t1, scause
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# uimm12
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# CHECK-INST: csrrs t2, scause, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x14]
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# CHECK-INST-ALIAS: csrr t2, scause
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# name
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csrrs t1, scause, zero
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# uimm12
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csrrs t2, 0x142, zero
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# stval
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# name
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# CHECK-INST: csrrs t1, stval, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x30,0x14]
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# CHECK-INST-ALIAS: csrr t1, stval
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# uimm12
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# CHECK-INST: csrrs t2, stval, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x14]
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# CHECK-INST-ALIAS: csrr t2, stval
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# aliases
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# aliases with uimm12
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# name
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csrrs t1, stval, zero
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# uimm12
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csrrs t2, 0x143, zero
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# sip
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# name
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# CHECK-INST: csrrs t1, sip, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x40,0x14]
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# CHECK-INST-ALIAS: csrr t1, sip
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# uimm12
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# CHECK-INST: csrrs t2, sip, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x14]
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# CHECK-INST-ALIAS: csrr t2, sip
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csrrs t1, sip, zero
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# uimm12
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csrrs t2, 0x144, zero
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#########################################
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# Supervisor Protection and Translation
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#########################################
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# satp
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# name
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# CHECK-INST: csrrs t1, satp, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0x18]
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# CHECK-INST-ALIAS: csrr t1, satp
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# uimm12
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# CHECK-INST: csrrs t2, satp, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x18]
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# CHECK-INST-ALIAS: csrr t2, satp
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# name
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csrrs t1, satp, zero
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# uimm12
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csrrs t2, 0x180, zero
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#########################################
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# Quality-of-Service(QoS) Identifiers
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#########################################
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# srmcfg
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# name
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# CHECK-INST: csrrs t1, srmcfg, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0x18]
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# CHECK-INST-ALIAS: csrr t1, srmcfg
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# uimm12
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# CHECK-INST: csrrs t2, srmcfg, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x18]
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# CHECK-INST-ALIAS: csrr t2, srmcfg
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# name
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csrrs t1, srmcfg, zero
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# uimm12
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csrrs t2, 0x181, zero
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#########################################
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# Debug/Trace Registers
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#########################################
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# scontext
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# name
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# CHECK-INST: csrrs t1, scontext, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x80,0x5a]
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# CHECK-INST-ALIAS: csrr t1, scontext
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# uimm12
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# CHECK-INST: csrrs t2, scontext, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x5a]
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# CHECK-INST-ALIAS: csrr t2, scontext
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# name
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csrrs t1, scontext, zero
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# uimm12
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csrrs t2, 0x5A8, zero
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#########################################
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# Supervisor Count Overflow (Sscofpmf)
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#########################################
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# scountovf
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# name
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# CHECK-INST: csrrs t1, scountovf, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0xda]
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# CHECK-INST-ALIAS: csrr t1, scountovf
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# uimm12
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# CHECK-INST: csrrs t2, scountovf, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xda]
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# CHECK-INST-ALIAS: csrr t2, scountovf
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# name
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csrrs t1, scountovf, zero
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# uimm12
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csrrs t2, 0xDA0, zero
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#########################################
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# State Enable Extension (Smstateen)
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#########################################
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# sstateen0
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# name
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# CHECK-INST: csrrs t1, sstateen0, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x10]
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# CHECK-INST-ALIAS: csrr t1, sstateen0
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# uimm12
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# CHECK-INST: csrrs t2, sstateen0, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x10]
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# CHECK-INST-ALIAS: csrr t2, sstateen0
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# name
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csrrs t1, sstateen0, zero
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# uimm12
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csrrs t2, 0x10C, zero
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# sstateen1
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# name
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# CHECK-INST: csrrs t1, sstateen1, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x10]
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# CHECK-INST-ALIAS: csrr t1, sstateen1
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# uimm12
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# CHECK-INST: csrrs t2, sstateen1, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x10]
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# CHECK-INST-ALIAS: csrr t2, sstateen1
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# name
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csrrs t1, sstateen1, zero
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# uimm12
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csrrs t2, 0x10D, zero
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# sstateen2
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# name
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# CHECK-INST: csrrs t1, sstateen2, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x10]
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# CHECK-INST-ALIAS: csrr t1, sstateen2
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# uimm12
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# CHECK-INST: csrrs t2, sstateen2, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x10]
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# CHECK-INST-ALIAS: csrr t2, sstateen2
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# name
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csrrs t1, sstateen2, zero
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# uimm12
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csrrs t2, 0x10E, zero
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# sstateen3
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# name
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# CHECK-INST: csrrs t1, sstateen3, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x10]
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# CHECK-INST-ALIAS: csrr t1, sstateen3
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# uimm12
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# CHECK-INST: csrrs t2, sstateen3, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x10]
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# CHECK-INST-ALIAS: csrr t2, sstateen3
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# name
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csrrs t1, sstateen3, zero
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# uimm12
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csrrs t2, 0x10F, zero
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#########################################
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# Advanced Interrupt Architecture (Smaia and Ssaia)
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#########################################
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# siselect
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# name
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# CHECK-INST: csrrs t1, siselect, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0x15]
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# CHECK-INST-ALIAS: csrr t1, siselect
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# uimm12
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# CHECK-INST: csrrs t2, siselect, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x15]
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# CHECK-INST-ALIAS: csrr t2, siselect
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# name
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csrrs t1, siselect, zero
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# uimm12
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csrrs t2, 0x150, zero
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# sireg
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# name
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# CHECK-INST: csrrs t1, sireg, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0x15]
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# CHECK-INST-ALIAS: csrr t1, sireg
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# uimm12
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# CHECK-INST: csrrs t2, sireg, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x15]
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# CHECK-INST-ALIAS: csrr t2, sireg
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# name
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csrrs t1, sireg, zero
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# uimm12
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csrrs t2, 0x151, zero
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# sireg2
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# name
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# CHECK-INST: csrrs t1, sireg2, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x20,0x15]
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# CHECK-INST-ALIAS: csrr t1, sireg2
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# uimm12
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# CHECK-INST: csrrs t2, sireg2, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x15]
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# CHECK-INST-ALIAS: csrr t2, sireg2
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# name
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csrrs t1, sireg2, zero
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# uimm12
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csrrs t2, 0x152, zero
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# sireg3
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# name
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# CHECK-INST: csrrs t1, sireg3, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x30,0x15]
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# CHECK-INST-ALIAS: csrr t1, sireg3
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# uimm12
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# CHECK-INST: csrrs t2, sireg3, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x15]
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# CHECK-INST-ALIAS: csrr t2, sireg3
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# name
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csrrs t1, sireg3, zero
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# uimm12
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csrrs t2, 0x153, zero
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# sireg4
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# name
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# CHECK-INST: csrrs t1, sireg4, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x50,0x15]
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# CHECK-INST-ALIAS: csrr t1, sireg4
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# uimm12
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# CHECK-INST: csrrs t2, sireg4, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x15]
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# CHECK-INST-ALIAS: csrr t2, sireg4
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# name
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csrrs t1, sireg4, zero
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# uimm12
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csrrs t2, 0x155, zero
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# sireg5
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# name
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# CHECK-INST: csrrs t1, sireg5, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x60,0x15]
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# CHECK-INST-ALIAS: csrr t1, sireg5
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# uimm12
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# CHECK-INST: csrrs t2, sireg5, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x15]
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# CHECK-INST-ALIAS: csrr t2, sireg5
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# name
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csrrs t1, sireg5, zero
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# uimm12
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csrrs t2, 0x156, zero
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# sireg6
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# name
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# CHECK-INST: csrrs t1, sireg6, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x70,0x15]
|
|
# CHECK-INST-ALIAS: csrr t1, sireg6
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, sireg6, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x15]
|
|
# CHECK-INST-ALIAS: csrr t2, sireg6
|
|
# name
|
|
csrrs t1, sireg6, zero
|
|
# uimm12
|
|
csrrs t2, 0x157, zero
|
|
|
|
# stopei
|
|
# name
|
|
# CHECK-INST: csrrs t1, stopei, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x15]
|
|
# CHECK-INST-ALIAS: csrr t1, stopei
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, stopei, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x15]
|
|
# CHECK-INST-ALIAS: csrr t2, stopei
|
|
# name
|
|
csrrs t1, stopei, zero
|
|
# uimm12
|
|
csrrs t2, 0x15C, zero
|
|
|
|
# stopi
|
|
# name
|
|
# CHECK-INST: csrrs t1, stopi, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x00,0xdb]
|
|
# CHECK-INST-ALIAS: csrr t1, stopi
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, stopi, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xdb]
|
|
# CHECK-INST-ALIAS: csrr t2, stopi
|
|
# name
|
|
csrrs t1, stopi, zero
|
|
# uimm12
|
|
csrrs t2, 0xDB0, zero
|
|
|
|
#########################################
|
|
# Counter Configuration (Ssccfg)
|
|
#########################################
|
|
|
|
# scountinhibit
|
|
# name
|
|
# CHECK-INST: csrrs t1, scountinhibit, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x12]
|
|
# CHECK-INST-ALIAS: csrr t1, scountinhibit
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, scountinhibit, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x12]
|
|
# CHECK-INST-ALIAS: csrr t2, scountinhibit
|
|
# name
|
|
csrrs t1, scountinhibit, zero
|
|
# uimm12
|
|
csrrs t2, 0x120, zero
|
|
|
|
##################################
|
|
# Control Transfer Records
|
|
##################################
|
|
|
|
# sctrctl
|
|
# name
|
|
# CHECK-INST: csrrs t1, sctrctl, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x14]
|
|
# CHECK-INST-ALIAS: csrr t1, sctrctl
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, sctrctl, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x14]
|
|
# CHECK-INST-ALIAS: csrr t2, sctrctl
|
|
csrrs t1, sctrctl, zero
|
|
# uimm12
|
|
csrrs t2, 0x14E, zero
|
|
|
|
# sctrstatus
|
|
# name
|
|
# CHECK-INST: csrrs t1, sctrstatus, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x14]
|
|
# CHECK-INST-ALIAS: csrr t1, sctrstatus
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, sctrstatus, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x14]
|
|
# CHECK-INST-ALIAS: csrr t2, sctrstatus
|
|
csrrs t1, sctrstatus, zero
|
|
# uimm12
|
|
csrrs t2, 0x14F, zero
|
|
|
|
# sctrdepth
|
|
# name
|
|
# CHECK-INST: csrrs t1, sctrdepth, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x15]
|
|
# CHECK-INST-ALIAS: csrr t1, sctrdepth
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, sctrdepth, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x15]
|
|
# CHECK-INST-ALIAS: csrr t2, sctrdepth
|
|
csrrs t1, sctrdepth, zero
|
|
# uimm12
|
|
csrrs t2, 0x15F, zero
|