derek.holloway
7502bf64a4
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37 lines
1.0 KiB
ArmAsm
37 lines
1.0 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: --mattr=+xqcili,+xqcilb,+xqcibi \
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# RUN: -riscv-add-build-attributes \
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# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INSTR %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
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# RUN: --mattr=+xqcili,+xqcilb,+xqcibi \
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# RUN: | llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL
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## This checks that, if the assembler can resolve the qc fixup, that the fixup
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## is applied correctly to the instruction.
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.L0:
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# CHECK-INSTR: qc.e.beqi a0, 64, 0x0
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qc.e.beqi a0, 64, .L0
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# CHECK-INSTR: qc.e.j 0x10000016
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qc.e.j func
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# CHECK-INSTR: qc.e.li a0, 8
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qc.e.li a0, abs_sym
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# CHECK-INSTR: qc.li a0, 8
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qc.li a0, %qc.abs20(abs_sym)
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# This has to come after the instructions that use it or it will
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# be evaluated at parse-time (avoiding fixups)
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abs_sym = 8
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.space 0x10000000
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func:
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ret
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## All these fixups should be resolved by the assembler without emitting
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## relocations.
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# CHECK-REL-NOT: R_RISCV
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