derek.holloway
7502bf64a4
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110 lines
3.2 KiB
ArmAsm
110 lines
3.2 KiB
ArmAsm
# RUN: llvm-mc -triple riscv32 -mattr=+xqcibi %s \
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# RUN: | FileCheck -check-prefix=ASM %s
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# RUN: llvm-mc -triple riscv32 -mattr=+xqcibi %s \
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# RUN: -filetype=obj -o - \
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# RUN: | llvm-objdump -dr --mattr=+xqcibi - \
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# RUN: | FileCheck -check-prefix=OBJ %s
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## This test checks that we emit the right relocations for Xqcibi
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## relative branches. These can be resolved within the same section
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## (when relaxations are disabled) but otherwise require a relocation.
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## The QC.E.B<op>I instructions also require a vendor relocation.
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# This is required so that the conditional branches requiring relocations
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# are not converted into inverted branches with long jumps by the assembler.
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.option exact
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# ASM-LABEL: this_section:
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# OBJ-LABEL: <this_section>:
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this_section:
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# ASM: qc.bnei t1, 10, undef
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# OBJ: qc.bnei t1, 0xa, 0x0 <this_section>
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# OBJ-NEXT: R_RISCV_BRANCH undef{{$}}
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qc.bnei t1, 10, undef
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# ASM: qc.e.bgeui s0, 20, undef
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# OBJ-NEXT: qc.e.bgeui s0, 0x14, 0x4 <this_section+0x4>
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# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
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# OBJ-NEXT: R_RISCV_QC_E_BRANCH undef{{$}}
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qc.e.bgeui s0, 20, undef
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# ASM: qc.bnei t2, 11, same_section
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# OBJ-NEXT: qc.bnei t2, 0xb, 0x28 <same_section>
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qc.bnei t2, 11, same_section
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# ASM: qc.e.bgeui s1, 21, same_section
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# OBJ-NEXT: qc.e.bgeui s1, 0x15, 0x28 <same_section>
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qc.e.bgeui s1, 21, same_section
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# ASM: qc.bnei t2, 12, same_section_extern
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# OBJ-NEXT: qc.bnei t2, 0xc, 0x14 <this_section+0x14>
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# OBJ-NEXT: R_RISCV_BRANCH same_section_extern{{$}}
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qc.bnei t2, 12, same_section_extern
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# ASM: qc.e.bgeui s1, 22, same_section_extern
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# OBJ-NEXT: qc.e.bgeui s1, 0x16, 0x18 <this_section+0x18>
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# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
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# OBJ-NEXT: R_RISCV_QC_E_BRANCH same_section_extern{{$}}
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qc.e.bgeui s1, 22, same_section_extern
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# ASM: qc.bnei t3, 13, other_section
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# OBJ-NEXT: qc.bnei t3, 0xd, 0x1e <this_section+0x1e>
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# OBJ-NEXT: R_RISCV_BRANCH other_section{{$}}
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qc.bnei t3, 13, other_section
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# ASM: qc.e.bgeui s2, 23, other_section
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# OBJ-NEXT: qc.e.bgeui s2, 0x17, 0x22 <this_section+0x22>
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# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
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# OBJ-NEXT: R_RISCV_QC_E_BRANCH other_section{{$}}
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qc.e.bgeui s2, 23, other_section
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# ASM-LABEL: same_section:
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# OBJ-LABEL: <same_section>:
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same_section:
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nop
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# ASM-LABEL: same_section_extern:
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# OBJ-LABEL: <same_section_extern>:
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.global same_section_extern
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same_section_extern:
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nop
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.option relax
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# ASM: qc.bnei t3, 14, same_section
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# OBJ: qc.bnei t3, 0xe, 0x28 <same_section>
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qc.bnei t3, 14, same_section
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# ASM: qc.e.bgeui s2, 24, same_section
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# OBJ-NEXT: qc.e.bgeui s2, 0x18, 0x28 <same_section>
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qc.e.bgeui s2, 24, same_section
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## Enable compression/relaxation to check how symbols are handled.
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.option noexact
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# ASM: qc.bnei t1, 10, undef
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# OBJ: qc.beqi t1, 0xa, 0x42 <same_section_extern+0x16>
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# OBJ-NEXT: j 0x3e <same_section_extern+0x12>
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# OBJ-NEXT: R_RISCV_JAL undef{{$}}
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# OBJ-NEXT: R_RISCV_RELAX *ABS*{{$}}
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qc.bnei t1, 10, undef
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# ASM: qc.e.bgeui s0, 40, undef
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# OBJ-NEXT: qc.e.bltui s0, 0x28, 0x4c <same_section_extern+0x20>
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# OBJ-NEXT: j 0x48 <same_section_extern+0x1c>
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# OBJ-NEXT: R_RISCV_JAL undef{{$}}
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# OBJ-NEXT: R_RISCV_RELAX *ABS*{{$}}
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qc.e.bgeui s0, 40, undef
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.section .text.second, "ax", @progbits
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# ASM-LABEL: other_section:
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# OBJ-LABEL: <other_section>:
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other_section:
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nop
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