derek.holloway
7502bf64a4
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45 lines
1.0 KiB
TableGen
45 lines
1.0 KiB
TableGen
include "llvm/Target/Target.td"
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class MyReg<string n> : Register<n> {
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let Namespace = "MyTarget";
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}
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"MyTarget", types, size, registers> {
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let Size = size;
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}
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def X0 : MyReg<"x0">;
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def X1 : MyReg<"x1">;
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def X2 : MyReg<"x2">;
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def X3 : MyReg<"x3">;
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def X4 : MyReg<"x4">;
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def X5 : MyReg<"x5">;
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def X6 : MyReg<"x6">;
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def XRegs : RegisterClass<"MyTarget", [i64], 64, (add X0, X1, X2, X3, X4, X5, X6)>;
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def Y0 : MyReg<"y0">;
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def Y1 : MyReg<"y1">;
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def Y2 : MyReg<"y2">;
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def Y3 : MyReg<"y3">;
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def Y4 : MyReg<"y4">;
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def Y5 : MyReg<"y5">;
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def Y6 : MyReg<"y6">;
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def YRegs : RegisterClass<"MyTarget", [i64], 64, (add Y0, Y1, Y2, Y3, Y4, Y5, Y6)>;
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class TestInstruction : Instruction {
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let Size = 2;
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let Namespace = "MyTarget";
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let hasSideEffects = false;
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let hasExtraSrcRegAllocReq = false;
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let hasExtraDefRegAllocReq = false;
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field bits<16> Inst;
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bits<3> dst;
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bits<3> src;
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bits<3> opcode;
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let Inst{2-0} = dst;
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let Inst{5-3} = src;
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let Inst{7-5} = opcode;
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}
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