derek.holloway
7502bf64a4
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76 lines
2.5 KiB
TableGen
76 lines
2.5 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o - 2>&1 >/dev/null | FileCheck %s
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include "llvm/Target/Target.td"
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def HasFeat : Predicate<"Subtarget->hasFeat()">;
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def TestMode : HwMode<[HasFeat]>;
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class MyReg<string n>
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: Register<n> {
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let Namespace = "Test";
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}
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"Test", types, size, registers> {
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let Size = size;
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}
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def X0 : MyReg<"x0">;
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def X1 : MyReg<"x1">;
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def X2 : MyReg<"x2">;
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def X3 : MyReg<"x3">;
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def X4 : MyReg<"x4">;
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def X5 : MyReg<"x5">;
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def X6 : MyReg<"x6">;
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def X7 : MyReg<"x7">;
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def X8 : MyReg<"x8">;
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def X9 : MyReg<"x9">;
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def X10 : MyReg<"x10">;
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def X11 : MyReg<"x11">;
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def X12 : MyReg<"x12">;
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def X13 : MyReg<"x13">;
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def X14 : MyReg<"x14">;
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def X15 : MyReg<"x15">;
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def ModeVT : ValueTypeByHwMode<[DefaultMode, TestMode],
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[i32, i64]>;
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let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>]> in
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def XRegs : MyClass<32, [ModeVT], (sequence "X%u", 0, 15)>;
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def sub_even : SubRegIndex<32> {
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let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],
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[SubRegRange<32>, SubRegRange<64>]>;
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}
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def sub_odd : SubRegIndex<32, 32> {
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let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],
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[SubRegRange<32, 32>, SubRegRange<64, 64>]>;
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}
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def XPairs : RegisterTuples<[sub_even, sub_odd],
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[(decimate (rotl XRegs, 0), 2),
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(decimate (rotl XRegs, 1), 2)]>;
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let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],
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[RegInfo<64,64,32>, RegInfo<128,128,64>]> in
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def XPairsClass : MyClass<64, [untyped], (add XPairs)>;
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def TestTarget : Target;
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// CHECK-LABEL: RegisterClass XRegs:
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// CHECK: SpillSize: { DefaultMode:32 TestMode:64 }
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// CHECK: SpillAlignment: { DefaultMode:32 TestMode:64 }
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// CHECK: Regs: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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// CHECK-LABEL: RegisterClass XPairsClass:
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// CHECK: SpillSize: { DefaultMode:64 TestMode:128 }
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// CHECK: SpillAlignment: { DefaultMode:32 TestMode:64 }
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// CHECK: CoveredBySubRegs: 1
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// CHECK: Regs: X0_X1 X2_X3 X4_X5 X6_X7 X8_X9 X10_X11 X12_X13 X14_X15
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// CHECK-LABEL: SubRegIndex sub_even:
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// CHECK: Offset: { DefaultMode:0 TestMode:0 }
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// CHECK: Size: { DefaultMode:32 TestMode:64 }
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// CHECK-LABEL: SubRegIndex sub_odd:
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// CHECK: Offset: { DefaultMode:32 TestMode:64 }
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// CHECK: Size: { DefaultMode:32 TestMode:64 }
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