TheRock/compiler/amd-llvm/llvm/test/Transforms/AggressiveInstCombine/AArch64/lower-table-based-log2-basics.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=aggressive-instcombine -mtriple=aarch64 -S < %s | FileCheck %s

;; These cases test lowering of various implementations of table-based log2
;; algorithms to the llvm.ctlz instruction.

;; C reproducers:
;; int log2(unsigned v) {
;;   static const unsigned char table[] = {
;;     0,  9,  1, 10, 13, 21,  2, 29, 11, 14, 16, 18, 22, 25,  3, 30,
;;     8, 12, 20, 28, 15, 17, 24,  7, 19, 27, 23,  6, 26,  5,  4, 31
;;   };
;;
;;   v |= v >> 1;
;;   v |= v >> 2;
;;   v |= v >> 4;
;;   v |= v >> 8;
;;   v |= v >> 16;
;;
;;   return table[(unsigned)(v * 0x07C4ACDDU) >> 27];
;; }
;; int log2_64(unsigned long long v) {
;;   static const unsigned char table[] = {
;;      0, 47,  1, 56, 48, 27,  2, 60, 57, 49, 41, 37, 28, 16,  3, 61,
;;     54, 58, 35, 52, 50, 42, 21, 44, 38, 32, 29, 23, 17, 11,  4, 62,
;;     46, 55, 26, 59, 40, 36, 15, 53, 34, 51, 20, 43, 31, 22, 10, 45,
;;     25, 39, 14, 33, 19, 30,  9, 24, 13, 18,  8, 12,  7,  6,  5, 63
;;   };
;;
;;   v |= v >> 1;
;;   v |= v >> 2;
;;   v |= v >> 4;
;;   v |= v >> 8;
;;   v |= v >> 16;
;;   v |= v >> 32;
;;
;;   return table[(v * 0x03F79D71B4CB0A89ULL) >> 58];
;; }

@log2.table = internal unnamed_addr constant [32 x i8] c"\00\09\01\0A\0D\15\02\1D\0B\0E\10\12\16\19\03\1E\08\0C\14\1C\0F\11\18\07\13\1B\17\06\1A\05\04\1F", align 1

define i32 @log2_32(i32 %v) !prof !0 {
; CHECK-LABEL: @log2_32(
; CHECK: !prof [[PROF0:![0-9]+]] {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[V:%.*]], i1 true)
; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 31, [[TMP0]]
; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[V]], 0
; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 0, i32 [[TMP1]], !prof [[PROF1:![0-9]+]]
; CHECK-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[TMP4]] to i32
; CHECK-NEXT:    ret i32 [[CONV]]
;
entry:
  %shr = lshr i32 %v, 1
  %or = or i32 %shr, %v
  %shr1 = lshr i32 %or, 2
  %or2 = or i32 %shr1, %or
  %shr3 = lshr i32 %or2, 4
  %or4 = or i32 %shr3, %or2
  %shr5 = lshr i32 %or4, 8
  %or6 = or i32 %shr5, %or4
  %shr7 = lshr i32 %or6, 16
  %or8 = or i32 %shr7, %or6
  %mul = mul i32 %or8, 130329821
  %shr9 = lshr i32 %mul, 27
  %idxprom = zext nneg i32 %shr9 to i64
  %arrayidx = getelementptr inbounds [32 x i8], ptr @log2.table, i64 0, i64 %idxprom
  %0 = load i8, ptr %arrayidx, align 1
  %conv = zext i8 %0 to i32
  ret i32 %conv
}

define i32 @log2_32_nusw(i32 %v) {
; CHECK-LABEL: @log2_32_nusw(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[V:%.*]], i1 true)
; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 31, [[TMP0]]
; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[V]], 0
; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 0, i32 [[TMP1]], !prof [[PROF1]]
; CHECK-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[TMP4]] to i32
; CHECK-NEXT:    ret i32 [[CONV]]
;
entry:
  %shr = lshr i32 %v, 1
  %or = or i32 %shr, %v
  %shr1 = lshr i32 %or, 2
  %or2 = or i32 %shr1, %or
  %shr3 = lshr i32 %or2, 4
  %or4 = or i32 %shr3, %or2
  %shr5 = lshr i32 %or4, 8
  %or6 = or i32 %shr5, %or4
  %shr7 = lshr i32 %or6, 16
  %or8 = or i32 %shr7, %or6
  %mul = mul i32 %or8, 130329821
  %shr9 = lshr i32 %mul, 27
  %idxprom = zext nneg i32 %shr9 to i64
  %arrayidx = getelementptr nusw [32 x i8], ptr @log2.table, i64 0, i64 %idxprom
  %0 = load i8, ptr %arrayidx, align 1
  %conv = zext i8 %0 to i32
  ret i32 %conv
}

@log2_64.table = internal unnamed_addr constant [64 x i8] c"\00/\0180\1B\02<91)%\1C\10\03=6:#42*\15,& \1D\17\11\0B\04>.7\1A;($\0F5\223\14+\1F\16\0A-\19'\0E!\13\1E\09\18\0D\12\08\0C\07\06\05?", align 1

define i32 @log2_64(i64 noundef %v) {
; CHECK-LABEL: @log2_64(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[V:%.*]], i1 true)
; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 63, [[TMP0]]
; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[V]], 0
; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i64 0, i64 [[TMP1]], !prof [[PROF1]]
; CHECK-NEXT:    [[TMP4:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[TMP4]] to i32
; CHECK-NEXT:    ret i32 [[CONV]]
;
entry:
  %shr = lshr i64 %v, 1
  %or = or i64 %shr, %v
  %shr1 = lshr i64 %or, 2
  %or2 = or i64 %shr1, %or
  %shr3 = lshr i64 %or2, 4
  %or4 = or i64 %shr3, %or2
  %shr5 = lshr i64 %or4, 8
  %or6 = or i64 %shr5, %or4
  %shr7 = lshr i64 %or6, 16
  %or8 = or i64 %shr7, %or6
  %shr9 = lshr i64 %or8, 32
  %or10 = or i64 %shr9, %or8
  %mul = mul i64 %or10, 285870213051386505
  %shr11 = lshr i64 %mul, 58
  %arrayidx = getelementptr inbounds i8, ptr @log2_64.table, i64 %shr11
  %0 = load i8, ptr %arrayidx, align 1
  %conv = zext i8 %0 to i32
  ret i32 %conv
}

@log2_16.table = internal unnamed_addr constant [16 x i8] c"\00\07\01\0D\08\0A\02\0E\06\0C\09\05\0B\04\03\0F", align 1

define i32 @log2_16(i16 noundef %0) {
; CHECK-LABEL: @log2_16(
; CHECK-NEXT:    [[TMP2:%.*]] = call i16 @llvm.ctlz.i16(i16 [[TMP0:%.*]], i1 true)
; CHECK-NEXT:    [[TMP3:%.*]] = sub i16 15, [[TMP2]]
; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i16 [[TMP0]], 0
; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i16 0, i16 [[TMP3]], !prof [[PROF1]]
; CHECK-NEXT:    [[TMP14:%.*]] = trunc i16 [[TMP5]] to i8
; CHECK-NEXT:    [[TMP15:%.*]] = zext i8 [[TMP14]] to i32
; CHECK-NEXT:    ret i32 [[TMP15]]
;
  %2 = lshr i16 %0, 1
  %3 = or i16 %2, %0
  %4 = lshr i16 %3, 2
  %5 = or i16 %4, %3
  %6 = lshr i16 %5, 4
  %7 = or i16 %6, %5
  %8 = lshr i16 %7, 8
  %9 = or i16 %8, %7
  %10 = mul i16 %9, 3885
  %11 = lshr i16 %10, 12
  %12 = zext nneg i16 %11 to i64
  %13 = getelementptr inbounds nuw i8, ptr @log2_16.table, i64 %12
  %14 = load i8, ptr %13, align 1
  %15 = zext i8 %14 to i32
  ret i32 %15
}


@log2_128.table = internal unnamed_addr constant [128 x i8] c"\00\0D\01\0E\13&\02\0F\1A\14A!'H\03\10\1E\1B9\15.B[\225(c<Ij\04}\11\18\1F\1C,3:\161/NCPU\\#E6g)Rdp=WJs^kw\05~\0C\12%\19@ G\1D8-Z4b;i|\17+20MOTDfQoVr]v\0B$?F7Yah{*LSenqu\0A>X`zKmt\09_yl\08x\07\06\7F", align 1

define i32 @log2_128(i128 noundef %0) {
; CHECK-LABEL: @log2_128(
; CHECK-NEXT:    [[TMP2:%.*]] = call i128 @llvm.ctlz.i128(i128 [[TMP0:%.*]], i1 true)
; CHECK-NEXT:    [[TMP3:%.*]] = sub i128 127, [[TMP2]]
; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i128 [[TMP0]], 0
; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i128 0, i128 [[TMP3]], !prof [[PROF1]]
; CHECK-NEXT:    [[TMP20:%.*]] = trunc i128 [[TMP5]] to i8
; CHECK-NEXT:    [[TMP21:%.*]] = zext i8 [[TMP20]] to i32
; CHECK-NEXT:    ret i32 [[TMP21]]
;
  %2 = lshr i128 %0, 1
  %3 = or i128 %2, %0
  %4 = lshr i128 %3, 2
  %5 = or i128 %4, %3
  %6 = lshr i128 %5, 4
  %7 = or i128 %6, %5
  %8 = lshr i128 %7, 8
  %9 = or i128 %8, %7
  %10 = lshr i128 %9, 16
  %11 = or i128 %10, %9
  %12 = lshr i128 %11, 32
  %13 = or i128 %12, %11
  %14 = lshr i128 %13, 64
  %15 = or i128 %14, %13
  %16 = mul i128 %15, 2638024179347461332462726661865453437
  %17 = lshr i128 %16, 121
  %18 = trunc nuw nsw i128 %17 to i64
  %19 = getelementptr inbounds nuw i8, ptr @log2_128.table, i64 %18
  %20 = load i8, ptr %19, align 1
  %21 = zext i8 %20 to i32
  ret i32 %21
}

!0 = !{!"function_entry_count", i64 1000}
; CHECK: [[PROF0]] = !{!"function_entry_count", i64 1000}
; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}