derek.holloway
7502bf64a4
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265 lines
10 KiB
LLVM
265 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=aggressive-instcombine -mtriple=x86_64 -mattr=+lzcnt -S < %s | FileCheck %s
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@log2.table = internal unnamed_addr constant [32 x i8] c"\05\09\01\0A\0D\15\02\1D\0B\0E\10\12\16\19\03\1E\08\0C\14\1C\0F\11\18\07\13\1B\17\06\1A\05\04\1F", align 1
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;; This is a negative test with a wrong table constant.
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define i32 @log2_32(i32 %v) {
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; CHECK-LABEL: @log2_32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
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; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 [[OR]], 2
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; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHR1]], [[OR]]
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; CHECK-NEXT: [[SHR3:%.*]] = lshr i32 [[OR2]], 4
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; CHECK-NEXT: [[OR4:%.*]] = or i32 [[SHR3]], [[OR2]]
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; CHECK-NEXT: [[SHR5:%.*]] = lshr i32 [[OR4]], 8
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; CHECK-NEXT: [[OR6:%.*]] = or i32 [[SHR5]], [[OR4]]
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; CHECK-NEXT: [[SHR7:%.*]] = lshr i32 [[OR6]], 16
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; CHECK-NEXT: [[OR8:%.*]] = or i32 [[SHR7]], [[OR6]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[OR8]], 130329821
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; CHECK-NEXT: [[SHR9:%.*]] = lshr i32 [[MUL]], 27
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext nneg i32 [[SHR9]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i8], ptr @log2.table, i64 0, i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP4]] to i32
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; CHECK-NEXT: ret i32 [[CONV]]
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;
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entry:
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%shr = lshr i32 %v, 1
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%or = or i32 %shr, %v
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%shr1 = lshr i32 %or, 2
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%or2 = or i32 %shr1, %or
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%shr3 = lshr i32 %or2, 4
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%or4 = or i32 %shr3, %or2
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%shr5 = lshr i32 %or4, 8
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%or6 = or i32 %shr5, %or4
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%shr7 = lshr i32 %or6, 16
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%or8 = or i32 %shr7, %or6
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%mul = mul i32 %or8, 130329821
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%shr9 = lshr i32 %mul, 27
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%idxprom = zext nneg i32 %shr9 to i64
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%arrayidx = getelementptr inbounds [32 x i8], ptr @log2.table, i64 0, i64 %idxprom
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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@log2_2.table = internal unnamed_addr constant [32 x i8] c"\00\09\01\0A\0D\15\02\1D\0B\0E\10\12\16\19\03\1E\08\0C\14\1C\0F\11\18\07\13\1B\17\06\1A\05\04\1F", align 1
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;; These are some negative tests with a wrong instruction sequences.
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define i32 @log2_32_2(i32 %v) {
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; CHECK-LABEL: @log2_32_2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
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; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 [[OR]], 2
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; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHR1]], [[OR]]
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; CHECK-NEXT: [[SHR3:%.*]] = lshr i32 [[OR2]], 4
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; CHECK-NEXT: [[OR4:%.*]] = or i32 [[SHR3]], [[OR2]]
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; CHECK-NEXT: [[SHR5:%.*]] = lshr i32 [[OR4]], 8
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; CHECK-NEXT: [[OR6:%.*]] = or i32 [[SHR5]], [[OR4]]
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; CHECK-NEXT: [[SHR7:%.*]] = lshr i32 [[OR6]], 15
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; CHECK-NEXT: [[OR8:%.*]] = or i32 [[SHR7]], [[OR6]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[OR8]], 130329821
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; CHECK-NEXT: [[SHR9:%.*]] = lshr i32 [[MUL]], 27
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext nneg i32 [[SHR9]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i8], ptr @log2_2.table, i64 0, i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
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; CHECK-NEXT: ret i32 [[CONV]]
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;
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entry:
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%shr = lshr i32 %v, 1
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%or = or i32 %shr, %v
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%shr1 = lshr i32 %or, 2
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%or2 = or i32 %shr1, %or
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%shr3 = lshr i32 %or2, 4
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%or4 = or i32 %shr3, %or2
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%shr5 = lshr i32 %or4, 8
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%or6 = or i32 %shr5, %or4
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%shr7 = lshr i32 %or6, 15
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%or8 = or i32 %shr7, %or6
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%mul = mul i32 %or8, 130329821
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%shr9 = lshr i32 %mul, 27
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%idxprom = zext nneg i32 %shr9 to i64
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%arrayidx = getelementptr inbounds [32 x i8], ptr @log2_2.table, i64 0, i64 %idxprom
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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define i32 @log2_32_3(i32 %v) {
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; CHECK-LABEL: @log2_32_3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
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; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 [[OR]], 2
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; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHR1]], [[OR]]
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; CHECK-NEXT: [[SHR3:%.*]] = lshr i32 [[OR2]], 4
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; CHECK-NEXT: [[OR4:%.*]] = or i32 [[SHR3]], [[OR2]]
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; CHECK-NEXT: [[SHR5:%.*]] = lshr i32 [[OR4]], 8
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; CHECK-NEXT: [[OR6:%.*]] = or i32 [[SHR5]], [[OR4]]
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; CHECK-NEXT: [[SHR7:%.*]] = lshr i32 [[OR6]], 16
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; CHECK-NEXT: [[OR8:%.*]] = or i32 [[SHR7]], [[OR6]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[OR8]], 130329822
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; CHECK-NEXT: [[SHR9:%.*]] = lshr i32 [[MUL]], 27
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext nneg i32 [[SHR9]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i8], ptr @log2_2.table, i64 0, i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
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; CHECK-NEXT: ret i32 [[CONV]]
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;
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entry:
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%shr = lshr i32 %v, 1
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%or = or i32 %shr, %v
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%shr1 = lshr i32 %or, 2
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%or2 = or i32 %shr1, %or
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%shr3 = lshr i32 %or2, 4
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%or4 = or i32 %shr3, %or2
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%shr5 = lshr i32 %or4, 8
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%or6 = or i32 %shr5, %or4
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%shr7 = lshr i32 %or6, 16
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%or8 = or i32 %shr7, %or6
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%mul = mul i32 %or8, 130329822
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%shr9 = lshr i32 %mul, 27
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%idxprom = zext nneg i32 %shr9 to i64
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%arrayidx = getelementptr inbounds [32 x i8], ptr @log2_2.table, i64 0, i64 %idxprom
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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define i32 @log2_32_4(i32 %v) {
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; CHECK-LABEL: @log2_32_4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
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; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 [[OR]], 2
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; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHR1]], [[OR]]
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; CHECK-NEXT: [[SHR3:%.*]] = lshr i32 [[OR2]], 4
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; CHECK-NEXT: [[OR4:%.*]] = or i32 [[SHR3]], [[OR2]]
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; CHECK-NEXT: [[SHR5:%.*]] = lshr i32 [[OR4]], 8
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; CHECK-NEXT: [[OR6:%.*]] = or i32 [[SHR5]], [[OR4]]
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; CHECK-NEXT: [[SHR7:%.*]] = lshr i32 [[OR6]], 15
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; CHECK-NEXT: [[OR8:%.*]] = or i32 [[SHR7]], [[OR6]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[OR8]], 130329821
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; CHECK-NEXT: [[SHR9:%.*]] = lshr i32 [[MUL]], 26
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext nneg i32 [[SHR9]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i8], ptr @log2_2.table, i64 0, i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
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; CHECK-NEXT: ret i32 [[CONV]]
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;
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entry:
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%shr = lshr i32 %v, 1
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%or = or i32 %shr, %v
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%shr1 = lshr i32 %or, 2
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%or2 = or i32 %shr1, %or
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%shr3 = lshr i32 %or2, 4
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%or4 = or i32 %shr3, %or2
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%shr5 = lshr i32 %or4, 8
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%or6 = or i32 %shr5, %or4
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%shr7 = lshr i32 %or6, 15
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%or8 = or i32 %shr7, %or6
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%mul = mul i32 %or8, 130329821
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%shr9 = lshr i32 %mul, 26
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%idxprom = zext nneg i32 %shr9 to i64
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%arrayidx = getelementptr inbounds [32 x i8], ptr @log2_2.table, i64 0, i64 %idxprom
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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;; A test with an extern global variable representing the table.
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@table = external global [32 x i8], align 1
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define i32 @log2_32_5(i32 %v) {
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; CHECK-LABEL: @log2_32_5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
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; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 [[OR]], 2
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; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHR1]], [[OR]]
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; CHECK-NEXT: [[SHR3:%.*]] = lshr i32 [[OR2]], 4
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; CHECK-NEXT: [[OR4:%.*]] = or i32 [[SHR3]], [[OR2]]
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; CHECK-NEXT: [[SHR5:%.*]] = lshr i32 [[OR4]], 8
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; CHECK-NEXT: [[OR6:%.*]] = or i32 [[SHR5]], [[OR4]]
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; CHECK-NEXT: [[SHR7:%.*]] = lshr i32 [[OR6]], 15
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; CHECK-NEXT: [[OR8:%.*]] = or i32 [[SHR7]], [[OR6]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[OR8]], 130329821
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; CHECK-NEXT: [[SHR9:%.*]] = lshr i32 [[MUL]], 26
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext nneg i32 [[SHR9]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i8], ptr @table, i64 0, i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
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; CHECK-NEXT: ret i32 [[CONV]]
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;
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entry:
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%shr = lshr i32 %v, 1
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%or = or i32 %shr, %v
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%shr1 = lshr i32 %or, 2
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%or2 = or i32 %shr1, %or
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%shr3 = lshr i32 %or2, 4
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%or4 = or i32 %shr3, %or2
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%shr5 = lshr i32 %or4, 8
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%or6 = or i32 %shr5, %or4
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%shr7 = lshr i32 %or6, 15
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%or8 = or i32 %shr7, %or6
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%mul = mul i32 %or8, 130329821
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%shr9 = lshr i32 %mul, 26
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%idxprom = zext nneg i32 %shr9 to i64
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%arrayidx = getelementptr inbounds [32 x i8], ptr @table, i64 0, i64 %idxprom
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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;; We want only constant tables to be considered as LOG2 ones.
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@log2_3.table = global [32 x i8] c"\00\09\01\0A\0D\15\02\1D\0B\0E\10\12\16\19\03\1E\08\0C\14\1C\0F\11\18\07\13\1B\17\06\1A\05\04\1F", align 1
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;; These are some negative tests with a wrong instruction sequences.
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define i32 @log2_32_6(i32 %v) {
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; CHECK-LABEL: @log2_32_6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[V]]
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; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 [[OR]], 2
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; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHR1]], [[OR]]
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; CHECK-NEXT: [[SHR3:%.*]] = lshr i32 [[OR2]], 4
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; CHECK-NEXT: [[OR4:%.*]] = or i32 [[SHR3]], [[OR2]]
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; CHECK-NEXT: [[SHR5:%.*]] = lshr i32 [[OR4]], 8
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; CHECK-NEXT: [[OR6:%.*]] = or i32 [[SHR5]], [[OR4]]
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; CHECK-NEXT: [[SHR7:%.*]] = lshr i32 [[OR6]], 15
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; CHECK-NEXT: [[OR8:%.*]] = or i32 [[SHR7]], [[OR6]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[OR8]], 130329821
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; CHECK-NEXT: [[SHR9:%.*]] = lshr i32 [[MUL]], 27
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext nneg i32 [[SHR9]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i8], ptr @log2_3.table, i64 0, i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
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; CHECK-NEXT: ret i32 [[CONV]]
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;
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entry:
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%shr = lshr i32 %v, 1
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%or = or i32 %shr, %v
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%shr1 = lshr i32 %or, 2
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%or2 = or i32 %shr1, %or
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%shr3 = lshr i32 %or2, 4
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%or4 = or i32 %shr3, %or2
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%shr5 = lshr i32 %or4, 8
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%or6 = or i32 %shr5, %or4
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%shr7 = lshr i32 %or6, 15
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%or8 = or i32 %shr7, %or6
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%mul = mul i32 %or8, 130329821
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%shr9 = lshr i32 %mul, 27
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%idxprom = zext nneg i32 %shr9 to i64
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%arrayidx = getelementptr inbounds [32 x i8], ptr @log2_3.table, i64 0, i64 %idxprom
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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