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TheRock/compiler/amd-llvm/llvm/test/Transforms/AggressiveInstCombine/umulh_ladder4.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

531 lines
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes=aggressive-instcombine,instcombine -S | FileCheck %s
; Ladder4 variant. https://alive2.llvm.org/ce/z/tExFRs
define i32 @mul_ladder4(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[X]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 32
; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i64 [[TMP3]] to i32
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %xl, %yl
%mullh = mul nuw i32 %xl, %yh
%mulhl = mul nuw i32 %xh, %yl
%mulhh = mul nuw i32 %xh, %yh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %shr8, %conv10
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %add, %conv12
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%add16 = add nuw i32 %mulhh, %shr15
%shr17 = lshr i32 %mulhl, 16
%add18 = add nuw i32 %add16, %shr17
%add19 = add nuw i32 %add18, %shr14
ret i32 %add19
}
define <2 x i32> @mul_ladder4_v2i32(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x i32> @mul_ladder4_v2i32(
; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = zext <2 x i32> [[X]] to <2 x i64>
; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[Y]] to <2 x i64>
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <2 x i64> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i64> [[TMP2]], splat (i64 32)
; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw <2 x i64> [[TMP3]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[ADD19]]
;
entry:
%xl = and <2 x i32> %x, <i32 65535, i32 65535>
%xh = lshr <2 x i32> %x, <i32 16, i32 16>
%yl = and <2 x i32> %y, <i32 65535, i32 65535>
%yh = lshr <2 x i32> %y, <i32 16, i32 16>
%mulll = mul nuw <2 x i32> %xl, %yl
%mullh = mul nuw <2 x i32> %xl, %yh
%mulhl = mul nuw <2 x i32> %xh, %yl
%mulhh = mul nuw <2 x i32> %xh, %yh
%shr8 = lshr <2 x i32> %mulll, <i32 16, i32 16>
%conv10 = and <2 x i32> %mullh, <i32 65535, i32 65535>
%add = add nuw nsw <2 x i32> %shr8, %conv10
%conv12 = and <2 x i32> %mulhl, <i32 65535, i32 65535>
%add13 = add nuw nsw <2 x i32> %add, %conv12
%shr14 = lshr <2 x i32> %add13, <i32 16, i32 16>
%shr15 = lshr <2 x i32> %mullh, <i32 16, i32 16>
%add16 = add nuw <2 x i32> %mulhh, %shr15
%shr17 = lshr <2 x i32> %mulhl, <i32 16, i32 16>
%add18 = add nuw <2 x i32> %add16, %shr17
%add19 = add nuw <2 x i32> %add18, %shr14
ret <2 x i32> %add19
}
define i128 @mul_ladder4_i128(i128 %x, i128 %y) {
; CHECK-LABEL: define i128 @mul_ladder4_i128(
; CHECK-SAME: i128 [[X:%.*]], i128 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = zext i128 [[X]] to i256
; CHECK-NEXT: [[TMP1:%.*]] = zext i128 [[Y]] to i256
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i256 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i256 [[TMP2]], 128
; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i256 [[TMP3]] to i128
; CHECK-NEXT: ret i128 [[ADD19]]
;
entry:
%xl = and i128 %x, u0xffffffffffffffff
%xh = lshr i128 %x, 64
%yl = and i128 %y, u0xffffffffffffffff
%yh = lshr i128 %y, 64
%mulll = mul nuw i128 %xl, %yl
%mullh = mul nuw i128 %xl, %yh
%mulhl = mul nuw i128 %xh, %yl
%mulhh = mul nuw i128 %xh, %yh
%shr8 = lshr i128 %mulll, 64
%conv10 = and i128 %mullh, u0xffffffffffffffff
%add = add nuw nsw i128 %shr8, %conv10
%conv12 = and i128 %mulhl, u0xffffffffffffffff
%add13 = add nuw nsw i128 %add, %conv12
%shr14 = lshr i128 %add13, 64
%shr15 = lshr i128 %mullh, 64
%add16 = add nuw i128 %mulhh, %shr15
%shr17 = lshr i128 %mulhl, 64
%add18 = add nuw i128 %add16, %shr17
%add19 = add nuw i128 %add18, %shr14
ret i128 %add19
}
define i32 @mul_ladder4_commutted(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_commutted(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[Y]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[X]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 32
; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i64 [[TMP3]] to i32
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %yl, %xl
%mullh = mul nuw i32 %yh, %xl
%mulhl = mul nuw i32 %yl, %xh
%mulhh = mul nuw i32 %yh, %xh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %conv10, %shr8
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %conv12, %add
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%shr17 = lshr i32 %mulhl, 16
%add16 = add nuw i32 %shr14, %shr17
%add18 = add nuw i32 %add16, %shr15
%add19 = add nuw i32 %mulhh, %add18
ret i32 %add19
}
define i32 @mul_ladder4_swap_hl_lh(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_swap_hl_lh(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[X]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 32
; CHECK-NEXT: [[ADD19:%.*]] = trunc nuw i64 [[TMP3]] to i32
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %xl, %yl
%mullh = mul nuw i32 %xl, %yh
%mulhl = mul nuw i32 %xh, %yl
%mulhh = mul nuw i32 %xh, %yh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mulhl, 65535
%add = add nuw nsw i32 %shr8, %conv10
%conv12 = and i32 %mullh, 65535
%add13 = add nuw nsw i32 %add, %conv12
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mulhl, 16
%add16 = add nuw i32 %mulhh, %shr15
%shr17 = lshr i32 %mullh, 16
%add18 = add nuw i32 %add16, %shr17
%add19 = add nuw i32 %add18, %shr14
ret i32 %add19
}
; Negative tests
define i32 @mul_ladder4_notlhhl(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_notlhhl(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535
; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16
; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535
; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16
; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[XL]], [[YL]]
; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[XH]], [[YL]]
; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[XH]], [[YH]]
; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16
; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[SHR8]], [[CONV10]]
; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[ADD]], [[CONV12]]
; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16
; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[ADD16:%.*]] = add nuw i32 [[MULHH]], [[SHR15]]
; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[ADD18:%.*]] = add nuw i32 [[ADD16]], [[SHR17]]
; CHECK-NEXT: [[ADD19:%.*]] = add nuw i32 [[ADD18]], [[SHR14]]
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %xl, %yl
%mullh = mul nuw i32 %xl, %yh
%mulhl = mul nuw i32 %xh, %yl
%mulhh = mul nuw i32 %xh, %yh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mulhl, 65535
%add = add nuw nsw i32 %shr8, %conv10
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %add, %conv12
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mulhl, 16
%add16 = add nuw i32 %mulhh, %shr15
%shr17 = lshr i32 %mulhl, 16
%add18 = add nuw i32 %add16, %shr17
%add19 = add nuw i32 %add18, %shr14
ret i32 %add19
}
; Extra uses
define i32 @mul_ladder4_use_add13(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_use_add13(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535
; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16
; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535
; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16
; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]
; CHECK-NEXT: [[MULLH:%.*]] = mul nuw i32 [[YH]], [[XL]]
; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]
; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]
; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16
; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULLH]], 65535
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV10]], [[SHR8]]
; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]
; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16
; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULLH]], 16
; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]
; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]
; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]
; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[ADD13]])
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %yl, %xl
%mullh = mul nuw i32 %yh, %xl
%mulhl = mul nuw i32 %yl, %xh
%mulhh = mul nuw i32 %yh, %xh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %conv10, %shr8
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %conv12, %add
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%shr17 = lshr i32 %mulhl, 16
%add16 = add i32 %shr14, %shr17
%add18 = add i32 %add16, %shr15
%add19 = add i32 %mulhh, %add18
call void (...) @llvm.fake.use(i32 %add13)
ret i32 %add19
}
define i32 @mul_ladder4_use_conv12(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_use_conv12(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535
; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16
; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535
; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16
; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]
; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YH]], [[XL]]
; CHECK-NEXT: [[MULHL1:%.*]] = mul nuw i32 [[YL]], [[XH]]
; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]
; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16
; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV12]], [[SHR8]]
; CHECK-NEXT: [[CONV13:%.*]] = and i32 [[MULHL1]], 65535
; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV13]], [[ADD]]
; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16
; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL1]], 16
; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]
; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]
; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]
; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[CONV13]])
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %yl, %xl
%mullh = mul nuw i32 %yh, %xl
%mulhl = mul nuw i32 %yl, %xh
%mulhh = mul nuw i32 %yh, %xh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %conv10, %shr8
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %conv12, %add
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%shr17 = lshr i32 %mulhl, 16
%add16 = add i32 %shr14, %shr17
%add18 = add i32 %add16, %shr15
%add19 = add i32 %mulhh, %add18
call void (...) @llvm.fake.use(i32 %conv12)
ret i32 %add19
}
define i32 @mul_ladder4_use_u0(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_use_u0(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535
; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16
; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535
; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16
; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]
; CHECK-NEXT: [[MULHL1:%.*]] = mul nuw i32 [[YH]], [[XL]]
; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]
; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]
; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16
; CHECK-NEXT: [[CONV13:%.*]] = and i32 [[MULHL1]], 65535
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV13]], [[SHR8]]
; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]
; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16
; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL1]], 16
; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]
; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]
; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]
; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[ADD]])
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %yl, %xl
%mullh = mul nuw i32 %yh, %xl
%mulhl = mul nuw i32 %yl, %xh
%mulhh = mul nuw i32 %yh, %xh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %conv10, %shr8
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %conv12, %add
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%shr17 = lshr i32 %mulhl, 16
%add16 = add i32 %shr14, %shr17
%add18 = add i32 %add16, %shr15
%add19 = add i32 %mulhh, %add18
call void (...) @llvm.fake.use(i32 %add)
ret i32 %add19
}
define i32 @mul_ladder4_use_hl(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_use_hl(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535
; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16
; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535
; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16
; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]
; CHECK-NEXT: [[MULLH:%.*]] = mul nuw i32 [[YH]], [[XL]]
; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]
; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]
; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16
; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULLH]], 65535
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV10]], [[SHR8]]
; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]
; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16
; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULLH]], 16
; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]
; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]
; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]
; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[MULHL]])
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %yl, %xl
%mullh = mul nuw i32 %yh, %xl
%mulhl = mul nuw i32 %yl, %xh
%mulhh = mul nuw i32 %yh, %xh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %conv10, %shr8
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %conv12, %add
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%shr17 = lshr i32 %mulhl, 16
%add16 = add i32 %shr14, %shr17
%add18 = add i32 %add16, %shr15
%add19 = add i32 %mulhh, %add18
call void (...) @llvm.fake.use(i32 %mulhl)
ret i32 %add19
}
define i32 @mul_ladder4_use_lh(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_use_lh(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535
; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16
; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535
; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16
; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]
; CHECK-NEXT: [[MULLH:%.*]] = mul nuw i32 [[YH]], [[XL]]
; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YL]], [[XH]]
; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]
; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16
; CHECK-NEXT: [[CONV10:%.*]] = and i32 [[MULLH]], 65535
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV10]], [[SHR8]]
; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV12]], [[ADD]]
; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16
; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULLH]], 16
; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]
; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]
; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]
; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[MULLH]])
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %yl, %xl
%mullh = mul nuw i32 %yh, %xl
%mulhl = mul nuw i32 %yl, %xh
%mulhh = mul nuw i32 %yh, %xh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %conv10, %shr8
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %conv12, %add
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%shr17 = lshr i32 %mulhl, 16
%add16 = add i32 %shr14, %shr17
%add18 = add i32 %add16, %shr15
%add19 = add i32 %mulhh, %add18
call void (...) @llvm.fake.use(i32 %mullh)
ret i32 %add19
}
define i32 @mul_ladder4_use_conv10(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @mul_ladder4_use_conv10(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[XL:%.*]] = and i32 [[X]], 65535
; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16
; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y]], 65535
; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16
; CHECK-NEXT: [[MULLL:%.*]] = mul nuw i32 [[YL]], [[XL]]
; CHECK-NEXT: [[MULHL:%.*]] = mul nuw i32 [[YH]], [[XL]]
; CHECK-NEXT: [[MULHL1:%.*]] = mul nuw i32 [[YL]], [[XH]]
; CHECK-NEXT: [[MULHH:%.*]] = mul nuw i32 [[YH]], [[XH]]
; CHECK-NEXT: [[SHR8:%.*]] = lshr i32 [[MULLL]], 16
; CHECK-NEXT: [[CONV12:%.*]] = and i32 [[MULHL]], 65535
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV12]], [[SHR8]]
; CHECK-NEXT: [[CONV13:%.*]] = and i32 [[MULHL1]], 65535
; CHECK-NEXT: [[ADD13:%.*]] = add nuw nsw i32 [[CONV13]], [[ADD]]
; CHECK-NEXT: [[SHR14:%.*]] = lshr i32 [[ADD13]], 16
; CHECK-NEXT: [[SHR15:%.*]] = lshr i32 [[MULHL]], 16
; CHECK-NEXT: [[SHR17:%.*]] = lshr i32 [[MULHL1]], 16
; CHECK-NEXT: [[ADD16:%.*]] = add nuw nsw i32 [[SHR14]], [[SHR17]]
; CHECK-NEXT: [[ADD18:%.*]] = add nuw nsw i32 [[ADD16]], [[SHR15]]
; CHECK-NEXT: [[ADD19:%.*]] = add i32 [[MULHH]], [[ADD18]]
; CHECK-NEXT: call void (...) @llvm.fake.use(i32 [[CONV12]])
; CHECK-NEXT: ret i32 [[ADD19]]
;
entry:
%xl = and i32 %x, 65535
%xh = lshr i32 %x, 16
%yl = and i32 %y, 65535
%yh = lshr i32 %y, 16
%mulll = mul nuw i32 %yl, %xl
%mullh = mul nuw i32 %yh, %xl
%mulhl = mul nuw i32 %yl, %xh
%mulhh = mul nuw i32 %yh, %xh
%shr8 = lshr i32 %mulll, 16
%conv10 = and i32 %mullh, 65535
%add = add nuw nsw i32 %conv10, %shr8
%conv12 = and i32 %mulhl, 65535
%add13 = add nuw nsw i32 %conv12, %add
%shr14 = lshr i32 %add13, 16
%shr15 = lshr i32 %mullh, 16
%shr17 = lshr i32 %mulhl, 16
%add16 = add i32 %shr14, %shr17
%add18 = add i32 %add16, %shr15
%add19 = add i32 %mulhh, %add18
call void (...) @llvm.fake.use(i32 %conv10)
ret i32 %add19
}
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