derek.holloway
7502bf64a4
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59 lines
1.7 KiB
LLVM
59 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm64-unknown-unknown -O3 < %s | FileCheck %s
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; This test should show that @f and @f_without_freeze generate equivalent
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; assembly
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; REQUIRES: aarch64-registered-target
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define void @f(ptr %p, i32 %n, i32 %m) {
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; CHECK-LABEL: f:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w8, w2, #1
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; CHECK-NEXT: .LBB0_1: // %loop
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: subs w1, w1, #1
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; CHECK-NEXT: strb wzr, [x0, w8, sxtw]
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; CHECK-NEXT: add w8, w8, #1
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; CHECK-NEXT: b.ne .LBB0_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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entry:
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br label %loop
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loop:
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%i = phi i32 [0, %entry], [%i.next, %loop]
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%i.next = add i32 %i, 1
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%i.next.fr = freeze i32 %i.next
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%j = add i32 %m, %i.next.fr
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%q = getelementptr i8, ptr %p, i32 %j
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store i8 0, ptr %q
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%cond = icmp eq i32 %i.next.fr, %n
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br i1 %cond, label %exit, label %loop
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exit:
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ret void
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}
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define void @f_without_freeze(ptr %p, i32 %n, i32 %m) {
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; CHECK-LABEL: f_without_freeze:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w8, w2, #1
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; CHECK-NEXT: .LBB1_1: // %loop
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: subs w1, w1, #1
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; CHECK-NEXT: strb wzr, [x0, w8, sxtw]
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; CHECK-NEXT: add w8, w8, #1
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; CHECK-NEXT: b.ne .LBB1_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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entry:
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br label %loop
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loop:
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%i = phi i32 [0, %entry], [%i.next, %loop]
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%i.next = add i32 %i, 1
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%j = add i32 %m, %i.next
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%q = getelementptr i8, ptr %p, i32 %j
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store i8 0, ptr %q
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%cond = icmp eq i32 %i.next, %n
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br i1 %cond, label %exit, label %loop
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exit:
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ret void
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}
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