derek.holloway
7502bf64a4
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128 lines
4.0 KiB
LLVM
128 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=consthoist -S < %s | FileCheck %s
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target triple = "x86_64--"
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; We don't want to convert constant divides because the benefit from converting
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; them to a mul in the backend is larget than constant materialization savings.
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define void @signed_const_division(i64 %in1, i64 %in2, ptr %addr) {
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; CHECK-LABEL: @signed_const_division(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[L1:%.*]] = phi i64 [ [[RES1:%.*]], [[LOOP]] ], [ [[IN1:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[L2:%.*]] = phi i64 [ [[RES2:%.*]], [[LOOP]] ], [ [[IN2:%.*]], [[ENTRY]] ]
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; CHECK-NEXT: [[RES1]] = sdiv i64 [[L1]], 4294967296
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; CHECK-NEXT: store volatile i64 [[RES1]], ptr [[ADDR:%.*]]
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; CHECK-NEXT: [[RES2]] = srem i64 [[L2]], 4294967296
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; CHECK-NEXT: store volatile i64 [[RES2]], ptr [[ADDR]]
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; CHECK-NEXT: [[AGAIN:%.*]] = icmp eq i64 [[RES1]], [[RES2]]
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; CHECK-NEXT: br i1 [[AGAIN]], label [[LOOP]], label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%l1 = phi i64 [%res1, %loop], [%in1, %entry]
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%l2 = phi i64 [%res2, %loop], [%in2, %entry]
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%res1 = sdiv i64 %l1, 4294967296
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store volatile i64 %res1, ptr %addr
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%res2 = srem i64 %l2, 4294967296
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store volatile i64 %res2, ptr %addr
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%again = icmp eq i64 %res1, %res2
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br i1 %again, label %loop, label %end
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end:
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ret void
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}
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define void @unsigned_const_division(i64 %in1, i64 %in2, ptr %addr) {
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; CHECK-LABEL: @unsigned_const_division(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[L1:%.*]] = phi i64 [ [[RES1:%.*]], [[LOOP]] ], [ [[IN1:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[L2:%.*]] = phi i64 [ [[RES2:%.*]], [[LOOP]] ], [ [[IN2:%.*]], [[ENTRY]] ]
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; CHECK-NEXT: [[RES1]] = udiv i64 [[L1]], 4294967296
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; CHECK-NEXT: store volatile i64 [[RES1]], ptr [[ADDR:%.*]]
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; CHECK-NEXT: [[RES2]] = urem i64 [[L2]], 4294967296
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; CHECK-NEXT: store volatile i64 [[RES2]], ptr [[ADDR]]
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; CHECK-NEXT: [[AGAIN:%.*]] = icmp eq i64 [[RES1]], [[RES2]]
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; CHECK-NEXT: br i1 [[AGAIN]], label [[LOOP]], label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%l1 = phi i64 [%res1, %loop], [%in1, %entry]
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%l2 = phi i64 [%res2, %loop], [%in2, %entry]
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%res1 = udiv i64 %l1, 4294967296
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store volatile i64 %res1, ptr %addr
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%res2 = urem i64 %l2, 4294967296
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store volatile i64 %res2, ptr %addr
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%again = icmp eq i64 %res1, %res2
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br i1 %again, label %loop, label %end
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end:
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ret void
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}
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define i32 @PR40934() {
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; CHECK-LABEL: @PR40934(
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; CHECK-NEXT: ret i32 undef
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; CHECK: bb:
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; CHECK-NEXT: [[T2:%.*]] = call i32 (i64, ...) @d(i64 7788015061)
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; CHECK-NEXT: [[T3:%.*]] = and i64 [[T3]], 7788015061
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; CHECK-NEXT: br label [[BB:%.*]]
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;
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ret i32 undef
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bb:
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%t2 = call i32 (i64, ...) @d(i64 7788015061)
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%t3 = and i64 %t3, 7788015061
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br label %bb
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}
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declare i32 @d(...)
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define i32 @PR40930() {
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; CHECK-LABEL: @PR40930(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: br label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: br label [[BB2]]
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; CHECK: bb3:
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; CHECK-NEXT: [[TMP4:%.*]] = call i32 (i64, i64, ...) @c(i64 4208870971, i64 4208870971)
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb5:
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP]], align 4
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; CHECK-NEXT: ret i32 [[TMP6]]
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;
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bb:
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%tmp = alloca i32, align 4
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br label %bb1
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bb1: ; preds = %bb3, %bb
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br label %bb2
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bb2: ; preds = %bb2, %bb1
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br label %bb2
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bb3: ; No predecessors!
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%tmp4 = call i32 (i64, i64, ...) @c(i64 4208870971, i64 4208870971)
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br label %bb1
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bb5: ; No predecessors!
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%tmp6 = load i32, ptr %tmp, align 4
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ret i32 %tmp6
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}
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declare i32 @c(...)
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