derek.holloway
7502bf64a4
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366 lines
20 KiB
LLVM
366 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -S -mtriple=aarch64-none-linux-gnu -mattr=+neon -passes=early-cse -earlycse-debug-hash | FileCheck %s
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; RUN: opt < %s -S -mtriple=aarch64-none-linux-gnu -mattr=+neon -aa-pipeline=basic-aa -passes='early-cse<memssa>' -verify-analysis-invalidation | FileCheck %s
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define <4 x i32> @test_cse(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
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; CHECK-LABEL: define <4 x i32> @test_cse(
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; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0
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; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1
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; CHECK-NEXT: br label %[[FOR_COND:.*]]
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; CHECK: [[FOR_COND]]:
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; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]
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; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]
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; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>
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; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { <4 x i32>, <4 x i32> } poison, <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = insertvalue { <4 x i32>, <4 x i32> } [[TMP2]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], 1
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; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])
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; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]])
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; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1
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; CHECK-NEXT: br label %[[FOR_COND]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: ret <4 x i32> [[RES_0]]
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;
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entry:
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; Check that @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
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%s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
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%s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
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br label %for.cond
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for.cond: ; preds = %for.body, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
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%cmp = icmp slt i32 %i.0, %n
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
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%1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
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%2 = bitcast <16 x i8> %0 to <4 x i32>
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%3 = bitcast <16 x i8> %1 to <4 x i32>
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call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
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%vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
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%vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
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%vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
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%call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end: ; preds = %for.cond
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ret <4 x i32> %res.0
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}
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define <4 x i32> @test_cse2(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
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; CHECK-LABEL: define <4 x i32> @test_cse2(
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; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0
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; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1
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; CHECK-NEXT: br label %[[FOR_COND:.*]]
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; CHECK: [[FOR_COND]]:
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; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]
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; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]
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; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>
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; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], ptr [[A]])
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; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { <4 x i32>, <4 x i32> } poison, <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = insertvalue { <4 x i32>, <4 x i32> } [[TMP2]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], 1
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; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])
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; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]])
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; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1
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; CHECK-NEXT: br label %[[FOR_COND]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: ret <4 x i32> [[RES_0]]
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;
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entry:
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; Check that the first @llvm.aarch64.neon.st2 is optimized away by Early CSE.
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%s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
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%s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
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br label %for.cond
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for.cond: ; preds = %for.body, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
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%cmp = icmp slt i32 %i.0, %n
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
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%1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
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%2 = bitcast <16 x i8> %0 to <4 x i32>
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%3 = bitcast <16 x i8> %1 to <4 x i32>
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call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %2, ptr %a)
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call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
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%vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
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%vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
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%vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
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%call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end: ; preds = %for.cond
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ret <4 x i32> %res.0
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}
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define <4 x i32> @test_cse3(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) #0 {
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; CHECK-LABEL: define <4 x i32> @test_cse3(
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; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[FOR_COND:.*]]
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; CHECK: [[FOR_COND]]:
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; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]
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; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]
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; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr [[A]])
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; CHECK-NEXT: [[VLD2_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2]], 0
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; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD2_FCA_0_EXTRACT]], <4 x i32> [[VLD2_FCA_0_EXTRACT]])
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; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1
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; CHECK-NEXT: br label %[[FOR_COND]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: ret <4 x i32> [[RES_0]]
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;
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entry:
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; Check that the first @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
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%s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
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%s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
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br label %for.cond
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for.cond: ; preds = %for.body, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
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%cmp = icmp slt i32 %i.0, %n
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
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%vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
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%vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
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%vld22 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
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%vld22.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld22, 0
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%vld22.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld22, 1
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%call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld22.fca.0.extract)
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end: ; preds = %for.cond
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ret <4 x i32> %res.0
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}
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define <4 x i32> @test_nocse(ptr %a, ptr %b, [2 x <4 x i32>] %s.coerce, i32 %n) {
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; CHECK-LABEL: define <4 x i32> @test_nocse(
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; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0
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; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1
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; CHECK-NEXT: br label %[[FOR_COND:.*]]
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; CHECK: [[FOR_COND]]:
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; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]
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; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]
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; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>
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; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])
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; CHECK-NEXT: store i32 0, ptr [[B]], align 4
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; CHECK-NEXT: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr [[A]])
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; CHECK-NEXT: [[VLD2_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2]], 0
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; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD2_FCA_0_EXTRACT]], <4 x i32> [[VLD2_FCA_0_EXTRACT]])
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; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1
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; CHECK-NEXT: br label %[[FOR_COND]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: ret <4 x i32> [[RES_0]]
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;
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entry:
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; Check that the store prevents @llvm.aarch64.neon.ld2 from being optimized
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; away by Early CSE.
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%s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
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%s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
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br label %for.cond
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for.cond: ; preds = %for.body, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
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%cmp = icmp slt i32 %i.0, %n
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
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%1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
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%2 = bitcast <16 x i8> %0 to <4 x i32>
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%3 = bitcast <16 x i8> %1 to <4 x i32>
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call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
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store i32 0, ptr %b, align 4
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%vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %a)
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%vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
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%vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
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%call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end: ; preds = %for.cond
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ret <4 x i32> %res.0
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}
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define <4 x i32> @test_nocse2(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
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; CHECK-LABEL: define <4 x i32> @test_nocse2(
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; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0
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; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1
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; CHECK-NEXT: br label %[[FOR_COND:.*]]
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; CHECK: [[FOR_COND]]:
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; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]
|
|
; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]
|
|
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]
|
|
; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]
|
|
; CHECK: [[FOR_BODY]]:
|
|
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>
|
|
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>
|
|
; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_1_EXTRACT]], ptr [[A]])
|
|
; CHECK-NEXT: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr [[A]])
|
|
; CHECK-NEXT: [[VLD3_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], 0
|
|
; CHECK-NEXT: [[VLD3_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], 2
|
|
; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD3_FCA_0_EXTRACT]], <4 x i32> [[VLD3_FCA_2_EXTRACT]])
|
|
; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1
|
|
; CHECK-NEXT: br label %[[FOR_COND]]
|
|
; CHECK: [[FOR_END]]:
|
|
; CHECK-NEXT: ret <4 x i32> [[RES_0]]
|
|
;
|
|
entry:
|
|
; Check that @llvm.aarch64.neon.ld3 is not optimized away by Early CSE due
|
|
; to mismatch between st2 and ld3.
|
|
%s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
|
|
%s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
|
|
br label %for.cond
|
|
|
|
for.cond: ; preds = %for.body, %entry
|
|
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
|
|
%res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
|
|
%cmp = icmp slt i32 %i.0, %n
|
|
br i1 %cmp, label %for.body, label %for.end
|
|
|
|
for.body: ; preds = %for.cond
|
|
%0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
|
|
%1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
|
|
%2 = bitcast <16 x i8> %0 to <4 x i32>
|
|
%3 = bitcast <16 x i8> %1 to <4 x i32>
|
|
call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
|
|
%vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %a)
|
|
%vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
|
|
%vld3.fca.2.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 2
|
|
%call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract)
|
|
%inc = add nsw i32 %i.0, 1
|
|
br label %for.cond
|
|
|
|
for.end: ; preds = %for.cond
|
|
ret <4 x i32> %res.0
|
|
}
|
|
|
|
define <4 x i32> @test_nocse3(ptr %a, [2 x <4 x i32>] %s.coerce, i32 %n) {
|
|
; CHECK-LABEL: define <4 x i32> @test_nocse3(
|
|
; CHECK-SAME: ptr [[A:%.*]], [2 x <4 x i32>] [[S_COERCE:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[ENTRY:.*]]:
|
|
; CHECK-NEXT: [[S_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 0
|
|
; CHECK-NEXT: [[S_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <4 x i32>] [[S_COERCE]], 1
|
|
; CHECK-NEXT: br label %[[FOR_COND:.*]]
|
|
; CHECK: [[FOR_COND]]:
|
|
; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY:.*]] ]
|
|
; CHECK-NEXT: [[RES_0:%.*]] = phi <4 x i32> [ undef, %[[ENTRY]] ], [ [[CALL:%.*]], %[[FOR_BODY]] ]
|
|
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]
|
|
; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_END:.*]]
|
|
; CHECK: [[FOR_BODY]]:
|
|
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_0_EXTRACT]] to <16 x i8>
|
|
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[S_COERCE_FCA_1_EXTRACT]] to <16 x i8>
|
|
; CHECK-NEXT: call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> [[S_COERCE_FCA_1_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], ptr [[A]])
|
|
; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> [[S_COERCE_FCA_0_EXTRACT]], <4 x i32> [[S_COERCE_FCA_0_EXTRACT]], ptr [[A]])
|
|
; CHECK-NEXT: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr [[A]])
|
|
; CHECK-NEXT: [[VLD3_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], 0
|
|
; CHECK-NEXT: [[CALL]] = call <4 x i32> @vaddq_s32(<4 x i32> [[VLD3_FCA_0_EXTRACT]], <4 x i32> [[VLD3_FCA_0_EXTRACT]])
|
|
; CHECK-NEXT: [[INC]] = add nsw i32 [[I_0]], 1
|
|
; CHECK-NEXT: br label %[[FOR_COND]]
|
|
; CHECK: [[FOR_END]]:
|
|
; CHECK-NEXT: ret <4 x i32> [[RES_0]]
|
|
;
|
|
entry:
|
|
; Check that @llvm.aarch64.neon.st3 is not optimized away by Early CSE due to
|
|
; mismatch between st2 and st3.
|
|
%s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0
|
|
%s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1
|
|
br label %for.cond
|
|
|
|
for.cond: ; preds = %for.body, %entry
|
|
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
|
|
%res.0 = phi <4 x i32> [ undef, %entry ], [ %call, %for.body ]
|
|
%cmp = icmp slt i32 %i.0, %n
|
|
br i1 %cmp, label %for.body, label %for.end
|
|
|
|
for.body: ; preds = %for.cond
|
|
%0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
|
|
%1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
|
|
%2 = bitcast <16 x i8> %0 to <4 x i32>
|
|
%3 = bitcast <16 x i8> %1 to <4 x i32>
|
|
call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> %3, <4 x i32> %2, <4 x i32> %2, ptr %a)
|
|
call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %2, ptr %a)
|
|
%vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %a)
|
|
%vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
|
|
%vld3.fca.1.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 1
|
|
%call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.0.extract)
|
|
%inc = add nsw i32 %i.0, 1
|
|
br label %for.cond
|
|
|
|
for.end: ; preds = %for.cond
|
|
ret <4 x i32> %res.0
|
|
}
|
|
|
|
define void @test_ld4_st4_no_cse(ptr %p, <16 x i8> %A, <16 x i8> %B) {
|
|
; CHECK-LABEL: define void @test_ld4_st4_no_cse(
|
|
; CHECK-SAME: ptr [[P:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[ENTRY:.*:]]
|
|
; CHECK-NEXT: [[LD:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0(ptr [[P]])
|
|
; CHECK-NEXT: [[EXT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[LD]], 0
|
|
; CHECK-NEXT: tail call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[EXT]], <16 x i8> [[A]], <16 x i8> [[B]], <16 x i8> zeroinitializer, ptr [[P]])
|
|
; CHECK-NEXT: ret void
|
|
;
|
|
entry:
|
|
%ld = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0(ptr %p)
|
|
%ext = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld, 0
|
|
tail call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> %ext, <16 x i8> %A, <16 x i8> %B, <16 x i8> zeroinitializer, ptr %p)
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: nounwind
|
|
declare void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32>, <4 x i32>, ptr nocapture)
|
|
|
|
; Function Attrs: nounwind
|
|
declare void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, ptr nocapture)
|
|
|
|
; Function Attrs: nounwind readonly
|
|
declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr)
|
|
|
|
; Function Attrs: nounwind readonly
|
|
declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr)
|
|
|
|
define internal fastcc <4 x i32> @vaddq_s32(<4 x i32> %__p0, <4 x i32> %__p1) {
|
|
; CHECK-LABEL: define internal fastcc <4 x i32> @vaddq_s32(
|
|
; CHECK-SAME: <4 x i32> [[__P0:%.*]], <4 x i32> [[__P1:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[ENTRY:.*:]]
|
|
; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[__P0]], [[__P1]]
|
|
; CHECK-NEXT: ret <4 x i32> [[ADD]]
|
|
;
|
|
entry:
|
|
%add = add <4 x i32> %__p0, %__p1
|
|
ret <4 x i32> %add
|
|
}
|