derek.holloway
7502bf64a4
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70 lines
3.3 KiB
LLVM
70 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=gvn -S -o - %s | FileCheck %s
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%struct.sk_buff = type opaque
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@l2tp_recv_dequeue_session = external dso_local local_unnamed_addr global i32, align 4
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@l2tp_recv_dequeue_skb = external dso_local local_unnamed_addr global ptr, align 8
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@l2tp_recv_dequeue_session_2 = external dso_local local_unnamed_addr global i32, align 4
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@l2tp_recv_dequeue_session_0 = external dso_local local_unnamed_addr global i32, align 4
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declare void @llvm.assume(i1 noundef)
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define dso_local void @l2tp_recv_dequeue() local_unnamed_addr {
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; CHECK-LABEL: define dso_local void @l2tp_recv_dequeue() local_unnamed_addr {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @l2tp_recv_dequeue_session, align 4
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; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = inttoptr i64 [[CONV]] to ptr
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @l2tp_recv_dequeue_session_2, align 4
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; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP2]], 0
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; CHECK-NEXT: br label %[[FOR_COND:.*]]
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; CHECK: [[FOR_COND]]:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi ptr [ [[TMP1]], %[[ENTRY]] ], [ null, %[[IF_END:.*]] ]
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; CHECK-NEXT: store ptr [[STOREMERGE]], ptr @l2tp_recv_dequeue_skb, align 8
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; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label %[[IF_END]], label %[[IF_THEN:.*]]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[STOREMERGE]], align 4
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; CHECK-NEXT: store i32 [[TMP3]], ptr @l2tp_recv_dequeue_session_0, align 4
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; CHECK-NEXT: callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"()
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; CHECK-NEXT: to label %[[ASM_FALLTHROUGH_I:.*]] [label %if.end]
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; CHECK: [[ASM_FALLTHROUGH_I]]:
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; CHECK-NEXT: br label %[[IF_END]]
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; CHECK: [[IF_END]]:
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[STOREMERGE]], align 4
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; CHECK-NEXT: [[TOBOOL2_NOT:%.*]] = icmp eq i32 [[TMP4]], 0
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TOBOOL2_NOT]])
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; CHECK-NEXT: br label %[[FOR_COND]]
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;
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entry:
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%0 = load i32, ptr @l2tp_recv_dequeue_session, align 4
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%conv = sext i32 %0 to i64
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%1 = inttoptr i64 %conv to ptr
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%2 = load i32, ptr @l2tp_recv_dequeue_session_2, align 4
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%tobool.not = icmp eq i32 %2, 0
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br label %for.cond
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for.cond: ; preds = %if.end, %entry
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%storemerge = phi ptr [ %1, %entry ], [ null, %if.end ]
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store ptr %storemerge, ptr @l2tp_recv_dequeue_skb, align 8
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br i1 %tobool.not, label %if.end, label %if.then
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if.then: ; preds = %for.cond
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%3 = load i32, ptr %storemerge, align 4
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store i32 %3, ptr @l2tp_recv_dequeue_session_0, align 4
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; Splitting the critical edge from if.then to if.end will fail, but should not
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; cause an infinite loop in GVN. If we can one day split edges of callbr
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; indirect targets, great!
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callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"()
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to label %asm.fallthrough.i [label %if.end]
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asm.fallthrough.i: ; preds = %if.then
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br label %if.end
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if.end: ; preds = %asm.fallthrough.i, %if.then, %for.cond
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%4 = load i32, ptr %storemerge, align 4
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%tobool2.not = icmp eq i32 %4, 0
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tail call void @llvm.assume(i1 %tobool2.not)
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br label %for.cond
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}
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