derek.holloway
7502bf64a4
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112 lines
5.8 KiB
LLVM
112 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -S -passes=gvn < %s | FileCheck %s
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define i32 @main(i64 %x, ptr %d, ptr noalias %p) {
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; CHECK-LABEL: define i32 @main(
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; CHECK-SAME: i64 [[X:%.*]], ptr [[D:%.*]], ptr noalias [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[T1_PRE_PRE_PRE:%.*]] = load ptr, ptr [[P]], align 8
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; CHECK-NEXT: [[T2_PRE_PRE_PRE:%.*]] = load ptr, ptr [[T1_PRE_PRE_PRE]], align 8, !tbaa [[ANYPTR_TBAA0:![0-9]+]]
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; CHECK-NEXT: [[T3_PRE_PRE_PRE:%.*]] = load ptr, ptr [[T2_PRE_PRE_PRE]], align 8
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[T2_PRE_PRE:%.*]] = phi ptr [ [[T2_PRE_PRE23:%.*]], %[[LOOP_LATCH:.*]] ], [ [[T2_PRE_PRE_PRE]], %[[ENTRY]] ]
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; CHECK-NEXT: [[T1_PRE_PRE:%.*]] = phi ptr [ [[T1_PRE_PRE19:%.*]], %[[LOOP_LATCH]] ], [ [[T1_PRE_PRE_PRE]], %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP2:.*]]
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; CHECK: [[LOOP2]]:
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; CHECK-NEXT: [[T2_PRE_PRE25:%.*]] = phi ptr [ [[T2_PRE_PRE23]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE:.*]] ], [ [[T2_PRE_PRE]], %[[LOOP]] ]
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; CHECK-NEXT: [[T1_PRE_PRE21:%.*]] = phi ptr [ [[T1_PRE_PRE19]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T1_PRE_PRE]], %[[LOOP]] ]
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; CHECK-NEXT: [[T3_PRE:%.*]] = phi ptr [ [[T3_PRE16:%.*]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T3_PRE_PRE_PRE]], %[[LOOP]] ]
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; CHECK-NEXT: [[T2_PRE:%.*]] = phi ptr [ [[T2_PRE13:%.*]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T2_PRE_PRE]], %[[LOOP]] ]
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; CHECK-NEXT: [[T1_PRE:%.*]] = phi ptr [ [[T1_PRE10:%.*]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T1_PRE_PRE]], %[[LOOP]] ]
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; CHECK-NEXT: br label %[[LOOP3:.*]]
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; CHECK: [[LOOP3]]:
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; CHECK-NEXT: [[T2_PRE_PRE24:%.*]] = phi ptr [ [[T2_PRE_PRE23]], %[[LOOP3_LATCH:.*]] ], [ [[T2_PRE_PRE25]], %[[LOOP2]] ]
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; CHECK-NEXT: [[T1_PRE_PRE20:%.*]] = phi ptr [ [[T1_PRE_PRE19]], %[[LOOP3_LATCH]] ], [ [[T1_PRE_PRE21]], %[[LOOP2]] ]
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; CHECK-NEXT: [[T3_PRE17:%.*]] = phi ptr [ [[T3_PRE16]], %[[LOOP3_LATCH]] ], [ [[T3_PRE]], %[[LOOP2]] ]
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; CHECK-NEXT: [[T2_PRE14:%.*]] = phi ptr [ [[T2_PRE13]], %[[LOOP3_LATCH]] ], [ [[T2_PRE]], %[[LOOP2]] ]
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; CHECK-NEXT: [[T1_PRE11:%.*]] = phi ptr [ [[T1_PRE10]], %[[LOOP3_LATCH]] ], [ [[T1_PRE]], %[[LOOP2]] ]
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; CHECK-NEXT: [[T78:%.*]] = phi ptr [ [[T7:%.*]], %[[LOOP3_LATCH]] ], [ [[T3_PRE]], %[[LOOP2]] ]
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; CHECK-NEXT: [[T66:%.*]] = phi ptr [ [[T6:%.*]], %[[LOOP3_LATCH]] ], [ [[T2_PRE]], %[[LOOP2]] ]
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; CHECK-NEXT: [[T54:%.*]] = phi ptr [ [[T5:%.*]], %[[LOOP3_LATCH]] ], [ [[T1_PRE]], %[[LOOP2]] ]
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; CHECK-NEXT: [[TOBOOL_NOT2_I:%.*]] = icmp eq i64 [[X]], 0
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; CHECK-NEXT: br i1 false, label %[[LOOP3_LOOP3_LATCH_CRIT_EDGE:.*]], label %[[FOR_BODY_LR_PH_I:.*]]
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; CHECK: [[LOOP3_LOOP3_LATCH_CRIT_EDGE]]:
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; CHECK-NEXT: br label %[[LOOP3_LATCH]]
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; CHECK: [[FOR_BODY_LR_PH_I]]:
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; CHECK-NEXT: store i32 0, ptr [[P]], align 4
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; CHECK-NEXT: [[T5_PRE:%.*]] = load ptr, ptr [[P]], align 8
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; CHECK-NEXT: [[T6_PRE:%.*]] = load ptr, ptr [[T5_PRE]], align 8, !tbaa [[ANYPTR_TBAA0]]
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; CHECK-NEXT: [[T7_PRE:%.*]] = load ptr, ptr [[T6_PRE]], align 8
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; CHECK-NEXT: br label %[[LOOP3_LATCH]]
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; CHECK: [[LOOP3_LATCH]]:
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; CHECK-NEXT: [[T2_PRE_PRE23]] = phi ptr [ [[T2_PRE_PRE24]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T6_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: [[T1_PRE_PRE19]] = phi ptr [ [[T1_PRE_PRE20]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T5_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: [[T3_PRE16]] = phi ptr [ [[T3_PRE17]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T7_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: [[T2_PRE13]] = phi ptr [ [[T2_PRE14]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T6_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: [[T1_PRE10]] = phi ptr [ [[T1_PRE11]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T5_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: [[T7]] = phi ptr [ [[T78]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T7_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: [[T6]] = phi ptr [ [[T66]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T6_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: [[T5]] = phi ptr [ [[T54]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T5_PRE]], %[[FOR_BODY_LR_PH_I]] ]
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; CHECK-NEXT: br i1 false, label %[[LOOP2_LATCH:.*]], label %[[LOOP3]]
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; CHECK: [[LOOP2_LATCH]]:
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; CHECK-NEXT: br i1 false, label %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]], label %[[LOOP_LATCH]]
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; CHECK: [[LOOP2_LATCH_LOOP2_CRIT_EDGE]]:
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; CHECK-NEXT: br label %[[LOOP2]]
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; CHECK: [[LOOP_LATCH]]:
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; CHECK-NEXT: store i32 0, ptr [[D]], align 4, !tbaa [[INT_TBAA4:![0-9]+]]
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; CHECK-NEXT: br label %[[LOOP]]
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;
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entry:
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br label %loop
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loop:
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br label %loop2
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loop2:
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br label %loop3
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loop3:
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%t1 = load ptr, ptr %p, align 8
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%t2 = load ptr, ptr %t1, align 8, !tbaa !0
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%t3 = load ptr, ptr %t2, align 8
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%t4 = load i8, ptr %t3, align 1
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%tobool.not2.i = icmp eq i64 %x, 0
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br i1 false, label %loop3.latch, label %for.body.lr.ph.i
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for.body.lr.ph.i:
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store i32 0, ptr %p, align 4
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br label %w.exit.loopexit
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w.exit.loopexit:
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br label %loop3.latch
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loop3.latch:
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%t5 = load ptr, ptr %p, align 8
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%t6 = load ptr, ptr %t5, align 8, !tbaa !0
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%t7 = load ptr, ptr %t6, align 8
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br i1 false, label %loop2.latch, label %loop3
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loop2.latch:
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br i1 false, label %loop2, label %loop.latch
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loop.latch:
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store i32 0, ptr %d, align 4, !tbaa !4
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br label %loop
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}
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!0 = !{!1, !1, i64 0}
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!1 = !{!"any pointer", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"int", !2, i64 0}
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;.
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; CHECK: [[ANYPTR_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
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; CHECK: [[META1]] = !{!"any pointer", [[META2:![0-9]+]], i64 0}
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; CHECK: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]], i64 0}
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; CHECK: [[META3]] = !{!"Simple C/C++ TBAA"}
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; CHECK: [[INT_TBAA4]] = !{[[META5:![0-9]+]], [[META5]], i64 0}
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; CHECK: [[META5]] = !{!"int", [[META2]], i64 0}
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;.
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