derek.holloway
7502bf64a4
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47 lines
1.9 KiB
LLVM
47 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes="gvn-sink" -S %s | FileCheck %s
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;; See https://github.com/llvm/llvm-project/issues/138345 for details.
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;; The program below used to crash due to taking the address of the inline asm.
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;; gvn-sink shouldn't do anything in this case, so test that the pass no longer
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;; generates invalid IR and no longer crashes.
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define void @c(i64 %num, ptr %ptr) {
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; CHECK-LABEL: define void @c(
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; CHECK-SAME: i64 [[NUM:%.*]], ptr [[PTR:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: switch i64 [[NUM]], label %[[SW_EPILOG:.*]] [
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; CHECK-NEXT: i64 1, label %[[SW_BB:.*]]
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; CHECK-NEXT: i64 0, label %[[SW_BB1:.*]]
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; CHECK-NEXT: ]
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; CHECK: [[SW_BB]]:
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; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[PTR]], align 1
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; CHECK-NEXT: call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 [[TMP1]], ptr @c)
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; CHECK-NEXT: br label %[[SW_EPILOG]]
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; CHECK: [[SW_BB1]]:
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; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[PTR]], align 1
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; CHECK-NEXT: call void asm sideeffect "movdqu 0 [[XMM0:%.*]] \0A\09", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 [[TMP2]], ptr @c)
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; CHECK-NEXT: br label %[[SW_EPILOG]]
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; CHECK: [[SW_EPILOG]]:
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; CHECK-NEXT: ret void
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;
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entry:
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switch i64 %num, label %sw.epilog [
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i64 1, label %sw.bb
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i64 0, label %sw.bb1
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]
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sw.bb: ; preds = %entry
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%1 = load i8, ptr %ptr, align 1
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call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 %1, ptr @c)
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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%2 = load i8, ptr %ptr, align 1
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call void asm sideeffect "movdqu 0 %xmm0 \0A\09", "r,r,~{dirflag},~{fpsr},~{flags}"(i8 %2, ptr @c)
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb1, %sw.bb, %entry
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ret void
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}
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