derek.holloway
7502bf64a4
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299 lines
11 KiB
LLVM
299 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals --include-generated-funcs
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; RUN: opt -mtriple=riscv32 -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s
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; REQUIRES: riscv-registered-target
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; This has two compatible regions based on function attributes. We have attributes
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; that should never be transferred to the outlined functions:
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; - `interrupt`=*
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; On RISC-V, the `interrupt` attribute only applies to the prolog and epilog of
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; the annotated function, and not any functions it calls. If this attribute is
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; preserved, there will be codegen errors because of restrictions on the
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; signatures of `interrupt` attributes.
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define void @outline_attrs1() #0 {
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entry:
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 2, ptr %a, align 4
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store i32 3, ptr %b, align 4
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store i32 4, ptr %c, align 4
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%al = load i32, ptr %a
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%bl = load i32, ptr %b
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%cl = load i32, ptr %c
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ret void
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}
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define void @outline_attrs2() #1 {
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entry:
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 2, ptr %a, align 4
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store i32 3, ptr %b, align 4
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store i32 4, ptr %c, align 4
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%al = load i32, ptr %a
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%bl = load i32, ptr %b
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%cl = load i32, ptr %c
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ret void
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}
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define void @outline_attrs3() {
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entry:
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 2, ptr %a, align 4
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store i32 3, ptr %b, align 4
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store i32 4, ptr %c, align 4
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%al = load i32, ptr %a
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%bl = load i32, ptr %b
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%cl = load i32, ptr %c
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ret void
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}
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define void @outline_outputs1() #0 {
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entry:
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%output = alloca i32, align 4
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%result = alloca i32, align 4
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%output2 = alloca i32, align 4
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%result2 = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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br label %block_2
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block_1:
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%a2 = alloca i32, align 4
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%b2 = alloca i32, align 4
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br label %block_2
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block_2:
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%a2val = load i32, ptr %a
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%b2val = load i32, ptr %b
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%add2 = add i32 2, %a2val
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%mul2 = mul i32 2, %b2val
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br label %block_5
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block_3:
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%aval = load i32, ptr %a
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%bval = load i32, ptr %b
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%add = add i32 2, %aval
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%mul = mul i32 2, %bval
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br label %block_4
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block_4:
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store i32 %add, ptr %output, align 4
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store i32 %mul, ptr %result, align 4
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br label %block_6
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block_5:
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store i32 %add2, ptr %output, align 4
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store i32 %mul2, ptr %result, align 4
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br label %block_7
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block_6:
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ret void
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block_7:
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ret void
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}
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define void @outline_outputs2() #1 {
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entry:
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%output = alloca i32, align 4
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%result = alloca i32, align 4
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%output2 = alloca i32, align 4
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%result2 = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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br label %block_2
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block_1:
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%a2 = alloca i32, align 4
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%b2 = alloca i32, align 4
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br label %block_2
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block_2:
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%a2val = load i32, ptr %a
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%b2val = load i32, ptr %b
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%add2 = add i32 2, %a2val
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%mul2 = mul i32 2, %b2val
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br label %block_5
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block_3:
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%aval = load i32, ptr %a
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%bval = load i32, ptr %b
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%add = add i32 2, %aval
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%mul = mul i32 2, %bval
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br label %block_4
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block_4:
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store i32 %add, ptr %output, align 4
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store i32 %mul, ptr %result, align 4
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br label %block_7
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block_5:
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store i32 %add2, ptr %output, align 4
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store i32 %mul2, ptr %result, align 4
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br label %block_6
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block_6:
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%diff = sub i32 %a2val, %b2val
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ret void
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block_7:
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%quot = udiv i32 %add, %mul
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ret void
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}
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attributes #0 = { "interrupt"="machine" optsize }
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attributes #1 = { "interrupt"="qci-nest" optsize }
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; CHECK-LABEL: define {{[^@]+}}@outline_attrs1
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; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
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; CHECK-NEXT: call void @outlined_ir_func_1(ptr [[A]], ptr [[B]], ptr [[C]])
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: define {{[^@]+}}@outline_attrs2
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; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
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; CHECK-NEXT: call void @outlined_ir_func_1(ptr [[A]], ptr [[B]], ptr [[C]])
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: define {{[^@]+}}@outline_attrs3() {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
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; CHECK-NEXT: call void @outlined_ir_func_1(ptr [[A]], ptr [[B]], ptr [[C]])
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: define {{[^@]+}}@outline_outputs1
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; CHECK-SAME: () #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2:%.*]]
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; CHECK: block_1:
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; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2]]
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; CHECK: block_2:
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; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[A]], ptr [[B]], ptr [[OUTPUT]], ptr [[RESULT]], ptr null, ptr null, ptr null, ptr null, i32 -1)
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; CHECK-NEXT: br i1 [[TMP0]], label [[BLOCK_6:%.*]], label [[BLOCK_7:%.*]]
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; CHECK: block_6:
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; CHECK-NEXT: ret void
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; CHECK: block_7:
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: define {{[^@]+}}@outline_outputs2
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; CHECK-SAME: () #[[ATTR1]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[ADD_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B2VAL_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[A2VAL_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2:%.*]]
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; CHECK: block_1:
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; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2]]
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; CHECK: block_2:
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; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[A2VAL_LOC]])
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; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[B2VAL_LOC]])
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; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[ADD_LOC]])
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; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[MUL_LOC]])
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; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[A]], ptr [[B]], ptr [[OUTPUT]], ptr [[RESULT]], ptr [[A2VAL_LOC]], ptr [[B2VAL_LOC]], ptr [[ADD_LOC]], ptr [[MUL_LOC]], i32 0)
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; CHECK-NEXT: [[A2VAL_RELOAD:%.*]] = load i32, ptr [[A2VAL_LOC]], align 4
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; CHECK-NEXT: [[B2VAL_RELOAD:%.*]] = load i32, ptr [[B2VAL_LOC]], align 4
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; CHECK-NEXT: [[ADD_RELOAD:%.*]] = load i32, ptr [[ADD_LOC]], align 4
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; CHECK-NEXT: [[MUL_RELOAD:%.*]] = load i32, ptr [[MUL_LOC]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[A2VAL_LOC]])
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; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[B2VAL_LOC]])
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; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[ADD_LOC]])
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; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[MUL_LOC]])
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; CHECK-NEXT: br i1 [[TMP0]], label [[BLOCK_7:%.*]], label [[BLOCK_6:%.*]]
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; CHECK: block_6:
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; CHECK-NEXT: [[DIFF:%.*]] = sub i32 [[A2VAL_RELOAD]], [[B2VAL_RELOAD]]
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; CHECK-NEXT: ret void
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; CHECK: block_7:
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; CHECK-NEXT: [[QUOT:%.*]] = udiv i32 [[ADD_RELOAD]], [[MUL_RELOAD]]
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: define {{[^@]+}}@outlined_ir_func_0
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; CHECK-SAME: (ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], ptr [[TMP2:%.*]], ptr [[TMP3:%.*]], ptr [[TMP4:%.*]], ptr [[TMP5:%.*]], ptr [[TMP6:%.*]], ptr [[TMP7:%.*]], i32 [[TMP8:%.*]]) #[[ATTR3:[0-9]+]] {
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; CHECK-NEXT: newFuncRoot:
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; CHECK-NEXT: br label [[BLOCK_2_TO_OUTLINE:%.*]]
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; CHECK: block_2_to_outline:
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; CHECK-NEXT: [[A2VAL:%.*]] = load i32, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[B2VAL:%.*]] = load i32, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[ADD2:%.*]] = add i32 2, [[A2VAL]]
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; CHECK-NEXT: [[MUL2:%.*]] = mul i32 2, [[B2VAL]]
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; CHECK-NEXT: br label [[BLOCK_5:%.*]]
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; CHECK: block_3:
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; CHECK-NEXT: [[AVAL:%.*]] = load i32, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[BVAL:%.*]] = load i32, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add i32 2, [[AVAL]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 2, [[BVAL]]
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; CHECK-NEXT: br label [[BLOCK_4:%.*]]
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; CHECK: block_4:
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; CHECK-NEXT: store i32 [[ADD]], ptr [[TMP2]], align 4
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; CHECK-NEXT: store i32 [[MUL]], ptr [[TMP3]], align 4
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; CHECK-NEXT: br label [[BLOCK_6_EXITSTUB:%.*]]
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; CHECK: block_5:
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; CHECK-NEXT: store i32 [[ADD2]], ptr [[TMP2]], align 4
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; CHECK-NEXT: store i32 [[MUL2]], ptr [[TMP3]], align 4
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; CHECK-NEXT: br label [[BLOCK_7_EXITSTUB:%.*]]
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; CHECK: block_6.exitStub:
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; CHECK-NEXT: switch i32 [[TMP8]], label [[FINAL_BLOCK_1:%.*]] [
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; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_1_1:%.*]]
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; CHECK-NEXT: ]
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; CHECK: block_7.exitStub:
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; CHECK-NEXT: switch i32 [[TMP8]], label [[FINAL_BLOCK_0:%.*]] [
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; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_1_0:%.*]]
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; CHECK-NEXT: ]
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; CHECK: output_block_1_0:
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; CHECK-NEXT: store i32 [[A2VAL]], ptr [[TMP4]], align 4
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; CHECK-NEXT: store i32 [[B2VAL]], ptr [[TMP5]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
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; CHECK: output_block_1_1:
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; CHECK-NEXT: store i32 [[ADD]], ptr [[TMP6]], align 4
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; CHECK-NEXT: store i32 [[MUL]], ptr [[TMP7]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_1]]
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; CHECK: final_block_0:
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; CHECK-NEXT: ret i1 false
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; CHECK: final_block_1:
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; CHECK-NEXT: ret i1 true
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;
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;
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; CHECK-LABEL: define {{[^@]+}}@outlined_ir_func_1
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; CHECK-SAME: (ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], ptr [[TMP2:%.*]]) #[[ATTR3]] {
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; CHECK-NEXT: newFuncRoot:
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; CHECK-NEXT: br label [[ENTRY_TO_OUTLINE:%.*]]
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; CHECK: entry_to_outline:
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; CHECK-NEXT: store i32 2, ptr [[TMP0]], align 4
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; CHECK-NEXT: store i32 3, ptr [[TMP1]], align 4
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; CHECK-NEXT: store i32 4, ptr [[TMP2]], align 4
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; CHECK-NEXT: [[AL:%.*]] = load i32, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[BL:%.*]] = load i32, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[CL:%.*]] = load i32, ptr [[TMP2]], align 4
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; CHECK-NEXT: br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
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; CHECK: entry_after_outline.exitStub:
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; CHECK-NEXT: ret void
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;
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;.
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; CHECK: attributes #[[ATTR0]] = { optsize "interrupt"="machine" }
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; CHECK: attributes #[[ATTR1]] = { optsize "interrupt"="qci-nest" }
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; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
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; CHECK: attributes #[[ATTR3]] = { minsize optsize }
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;.
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