derek.holloway
7502bf64a4
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220 lines
14 KiB
LLVM
220 lines
14 KiB
LLVM
; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
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; SVE intrinsics fmul, fmul_u, fadd, fadd_u, fsub and fsub_u should be replaced with regular fmul, fadd and fsub.
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declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fmul_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fmul_intrinsic_half
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; CHECK-NEXT: %1 = fmul fast <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fmul_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fmul_intrinsic_float
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; CHECK-NEXT: %1 = fmul fast <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fmul_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fmul_intrinsic_double
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; CHECK-NEXT: %1 = fmul fast <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fmul_u_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fmul_u_intrinsic_half
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; CHECK-NEXT: %1 = fmul fast <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fmul_u_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fmul_u_intrinsic_float
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; CHECK-NEXT: %1 = fmul fast <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fmul_u_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fmul_u_intrinsic_double
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; CHECK-NEXT: %1 = fmul fast <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fmul.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fadd_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fadd_intrinsic_half
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; CHECK-NEXT: %1 = fadd fast <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fadd_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fadd_intrinsic_float
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; CHECK-NEXT: %1 = fadd fast <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fadd_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fadd_intrinsic_double
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; CHECK-NEXT: %1 = fadd fast <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fadd_u_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fadd_u_intrinsic_half
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; CHECK-NEXT: %1 = fadd fast <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fadd_u_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fadd_u_intrinsic_float
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; CHECK-NEXT: %1 = fadd fast <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fadd_u_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fadd_u_intrinsic_double
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; CHECK-NEXT: %1 = fadd fast <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fadd.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fsub_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fsub_intrinsic_half
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; CHECK-NEXT: %1 = fsub fast <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fsub_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fsub_intrinsic_float
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; CHECK-NEXT: %1 = fsub fast <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fsub_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fsub_intrinsic_double
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; CHECK-NEXT: %1 = fsub fast <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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define <vscale x 2 x double> @no_replace_on_non_ptrue_all(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @no_replace_on_non_ptrue_all
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; CHECK-NEXT: %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)
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; CHECK-NEXT: %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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; CHECK-NEXT: ret <vscale x 2 x double> %2
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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define <vscale x 2 x double> @replace_fsub_intrinsic_no_fast_flag(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fsub_intrinsic_no_fast_flag
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; CHECK-NEXT: %1 = fsub <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fsub_u_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fsub_u_intrinsic_half
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; CHECK-NEXT: %1 = fsub fast <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fsub_u_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fsub_u_intrinsic_float
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; CHECK-NEXT: %1 = fsub fast <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fsub_u_intrinsic_no_fast_flag(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fsub_u_intrinsic_no_fast_flag
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; CHECK-NEXT: %1 = fsub <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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define <vscale x 2 x double> @no_replace_on_non_ptrue_all_u(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @no_replace_on_non_ptrue_all_u
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; CHECK-NEXT: %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)
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; CHECK-NEXT: %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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; CHECK-NEXT: ret <vscale x 2 x double> %2
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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attributes #0 = { "target-features"="+sve" }
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