derek.holloway
7502bf64a4
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351 lines
20 KiB
LLVM
351 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <vscale x 16 x i8> @constant_asr_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_0(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: ret <vscale x 16 x i8> splat (i8 7)
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))
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ret <vscale x 16 x i8> %r
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}
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define <vscale x 16 x i8> @constant_asr_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_1(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -32), <vscale x 16 x i8> splat (i8 -63)
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; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))
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ret <vscale x 16 x i8> %r
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}
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; data = 0x80
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define <vscale x 16 x i8> @constant_asr_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_7(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i8> splat (i8 -128)
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; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 7))
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ret <vscale x 16 x i8> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.
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; data = 0x80
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define <vscale x 16 x i8> @constant_asr_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_8(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 8))
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; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 8))
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ret <vscale x 16 x i8> %r
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}
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; data = 0x8000
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define <vscale x 8 x i16> @constant_asr_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 8 x i16> @constant_asr_i16_shift_by_15(
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; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i16> splat (i16 -32768)
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; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]
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;
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%r = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 15))
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ret <vscale x 8 x i16> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.
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; data = 0x8000
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define <vscale x 8 x i16> @constant_asr_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 8 x i16> @constant_asr_i16_shift_by_16(
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; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 16))
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; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]
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;
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%r = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 16))
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ret <vscale x 8 x i16> %r
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}
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; data = 0x800000000
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define <vscale x 4 x i32> @constant_asr_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_asr_i32_shift_by_31(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i32> splat (i32 -2147483648)
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 31))
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ret <vscale x 4 x i32> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.
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; data = 0x80000000
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define <vscale x 4 x i32> @constant_asr_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_asr_i32_shift_by_32(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 32))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 32))
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ret <vscale x 4 x i32> %r
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}
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; data = 0x8000000000000000
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define <vscale x 2 x i64> @constant_asr_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 2 x i64> @constant_asr_i64_shift_by_63(
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; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i64> splat (i64 -9223372036854775808)
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; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
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;
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%r = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 63))
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ret <vscale x 2 x i64> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.
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; data = 0x8000000000000000
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define <vscale x 2 x i64> @constant_asr_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 2 x i64> @constant_asr_i64_shift_by_64(
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; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 64))
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; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
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;
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%r = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 64))
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ret <vscale x 2 x i64> %r
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}
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define <vscale x 16 x i8> @constant_lsl_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_0(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: ret <vscale x 16 x i8> splat (i8 7)
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))
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ret <vscale x 16 x i8> %r
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}
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define <vscale x 16 x i8> @constant_lsl_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_1(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -126), <vscale x 16 x i8> splat (i8 -63)
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; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))
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ret <vscale x 16 x i8> %r
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}
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; result = 0x80
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define <vscale x 16 x i8> @constant_lsl_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_7(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 1)
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; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 7))
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ret <vscale x 16 x i8> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.
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define <vscale x 16 x i8> @constant_lsl_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_8(
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; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 8))
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; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
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;
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%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 8))
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ret <vscale x 16 x i8> %r
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}
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; result = 0x8000
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define <vscale x 8 x i16> @constant_lsl_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsl_i16_shift_by_15(
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; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 1)
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; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]
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;
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%r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 15))
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ret <vscale x 8 x i16> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.
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define <vscale x 8 x i16> @constant_lsl_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsl_i16_shift_by_16(
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; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 16))
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; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]
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;
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%r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 16))
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ret <vscale x 8 x i16> %r
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}
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; result = 0x800000000
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define <vscale x 4 x i32> @constant_lsl_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsl_i32_shift_by_31(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 1)
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 31))
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ret <vscale x 4 x i32> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.
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define <vscale x 4 x i32> @constant_lsl_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsl_i32_shift_by_32(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 32))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 32))
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ret <vscale x 4 x i32> %r
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}
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; result = 0x8000000000000000
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define <vscale x 2 x i64> @constant_lsl_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsl_i64_shift_by_63(
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; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 1)
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; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
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;
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%r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 63))
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ret <vscale x 2 x i64> %r
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}
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; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.
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define <vscale x 2 x i64> @constant_lsl_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsl_i64_shift_by_64(
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; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 64))
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; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
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;
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%r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 64))
|
|
ret <vscale x 2 x i64> %r
|
|
}
|
|
|
|
define <vscale x 16 x i8> @constant_lsr_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_0(
|
|
; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: ret <vscale x 16 x i8> splat (i8 7)
|
|
;
|
|
%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))
|
|
ret <vscale x 16 x i8> %r
|
|
}
|
|
|
|
define <vscale x 16 x i8> @constant_lsr_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_1(
|
|
; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 96), <vscale x 16 x i8> splat (i8 -63)
|
|
; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
|
|
;
|
|
%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))
|
|
ret <vscale x 16 x i8> %r
|
|
}
|
|
|
|
; data = 0x80
|
|
define <vscale x 16 x i8> @constant_lsr_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_7(
|
|
; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 -128)
|
|
; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
|
|
;
|
|
%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 7))
|
|
ret <vscale x 16 x i8> %r
|
|
}
|
|
|
|
; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.
|
|
; data = 0x80
|
|
define <vscale x 16 x i8> @constant_lsr_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_8(
|
|
; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 8))
|
|
; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]
|
|
;
|
|
%r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 8))
|
|
ret <vscale x 16 x i8> %r
|
|
}
|
|
|
|
; data = 0x8000
|
|
define <vscale x 8 x i16> @constant_lsr_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsr_i16_shift_by_15(
|
|
; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = select <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 -32768)
|
|
; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]
|
|
;
|
|
%r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 15))
|
|
ret <vscale x 8 x i16> %r
|
|
}
|
|
|
|
; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.
|
|
; data = 0x8000
|
|
define <vscale x 8 x i16> @constant_lsr_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsr_i16_shift_by_16(
|
|
; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 16))
|
|
; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]
|
|
;
|
|
%r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 16))
|
|
ret <vscale x 8 x i16> %r
|
|
}
|
|
|
|
; data = 0x800000000
|
|
define <vscale x 4 x i32> @constant_lsr_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsr_i32_shift_by_31(
|
|
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 -2147483648)
|
|
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
|
|
;
|
|
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 31))
|
|
ret <vscale x 4 x i32> %r
|
|
}
|
|
|
|
; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.
|
|
; data = 0x80000000
|
|
define <vscale x 4 x i32> @constant_lsr_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsr_i32_shift_by_32(
|
|
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 32))
|
|
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
|
|
;
|
|
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 32))
|
|
ret <vscale x 4 x i32> %r
|
|
}
|
|
|
|
; data = 0x8000000000000000
|
|
define <vscale x 2 x i64> @constant_lsr_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsr_i64_shift_by_63(
|
|
; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 -9223372036854775808)
|
|
; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
|
|
;
|
|
%r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 63))
|
|
ret <vscale x 2 x i64> %r
|
|
}
|
|
|
|
; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.
|
|
; data = 0x8000000000000000
|
|
define <vscale x 2 x i64> @constant_lsr_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {
|
|
; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsr_i64_shift_by_64(
|
|
; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
|
|
; CHECK-NEXT: [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 64))
|
|
; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
|
|
;
|
|
%r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 64))
|
|
ret <vscale x 2 x i64> %r
|
|
}
|
|
|
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
|
|
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
|
|
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|