TheRock/compiler/amd-llvm/llvm/test/Transforms/InstCombine/AMDGPU/mbcnt-negative-cases.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-codegenprepare < %s | FileCheck %s

; Test negative cases where mbcnt optimizations should NOT be applied

; =============================================================================
; NO WORK GROUP SIZE METADATA
; =============================================================================

; Test with no reqd_work_group_size
define i32 @test_mbcnt_no_work_group_size() {
; CHECK-LABEL: define i32 @test_mbcnt_no_work_group_size() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[A:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
; CHECK-NEXT:    [[B:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[A]])
; CHECK-NEXT:    ret i32 [[B]]
;
entry:
  %a = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
  %b = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %a)
  ret i32 %b
}

; Test mbcnt.lo with no work group size
define i32 @test_mbcnt_lo_no_work_group_size() {
; CHECK-LABEL: define i32 @test_mbcnt_lo_no_work_group_size() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[A:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
; CHECK-NEXT:    ret i32 [[A]]
;
entry:
  %a = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
  ret i32 %a
}

; =============================================================================
; PARTIAL MASKS AND NON-STANDARD PATTERNS
; =============================================================================

; Test with partial mask
define i32 @test_mbcnt_partial_mask() !reqd_work_group_size !0 {
; CHECK-LABEL: define i32 @test_mbcnt_partial_mask(
; CHECK-SAME: ) !reqd_work_group_size [[META0:![0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[A:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 65535, i32 0)
; CHECK-NEXT:    [[B:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[A]])
; CHECK-NEXT:    ret i32 [[B]]
;
entry:
  %a = call i32 @llvm.amdgcn.mbcnt.lo(i32 65535, i32 0)
  %b = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %a)
  ret i32 %b
}

; Test with non-zero base
define i32 @test_mbcnt_non_zero_base() !reqd_work_group_size !0 {
; CHECK-LABEL: define i32 @test_mbcnt_non_zero_base(
; CHECK-SAME: ) !reqd_work_group_size [[META0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[A:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 5)
; CHECK-NEXT:    [[B:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[A]])
; CHECK-NEXT:    ret i32 [[B]]
;
entry:
  %a = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 5)
  %b = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %a)
  ret i32 %b
}

; =============================================================================
; COPY OPTIMIZATION NEGATIVE CASES
; =============================================================================

; Test with no work group size
define i32 @test_mbcnt_hi_copy_no_wgs(i32 %val) {
; CHECK-LABEL: define i32 @test_mbcnt_hi_copy_no_wgs(
; CHECK-SAME: i32 [[VAL:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[RESULT:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[VAL]])
; CHECK-NEXT:    ret i32 [[RESULT]]
;
entry:
  %result = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %val)
  ret i32 %result
}

; Test with work group size = not a wave multiple (48)
define i32 @test_mbcnt_hi_copy_non_wave_multiple(i32 %val) !reqd_work_group_size !1 {
; CHECK-LABEL: define i32 @test_mbcnt_hi_copy_non_wave_multiple(
; CHECK-SAME: i32 [[VAL:%.*]]) !reqd_work_group_size [[META1:![0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[RESULT:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[VAL]])
; CHECK-NEXT:    ret i32 [[RESULT]]
;
entry:
  %result = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %val)
  ret i32 %result
}

; Test with zero mask
define i32 @test_mbcnt_hi_copy_zero_mask(i32 %val) !reqd_work_group_size !0 {
; CHECK-LABEL: define i32 @test_mbcnt_hi_copy_zero_mask(
; CHECK-SAME: i32 [[VAL:%.*]]) !reqd_work_group_size [[META0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[RESULT:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 [[VAL]])
; CHECK-NEXT:    ret i32 [[RESULT]]
;
entry:
  %result = call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 %val)
  ret i32 %result
}

; =============================================================================
; METADATA
; =============================================================================

!0 = !{i32 64, i32 1, i32 1}   ; X=64 (wave64 or 2*wave32)
!1 = !{i32 48, i32 1, i32 1}   ; X=48 (not wave multiple)

; =============================================================================
; FUNCTION DECLARATIONS
; =============================================================================

declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0

attributes #0 = { nounwind readnone speculatable willreturn }
;.
; CHECK: [[META0]] = !{i32 64, i32 1, i32 1}
; CHECK: [[META1]] = !{i32 48, i32 1, i32 1}
;.