derek.holloway
7502bf64a4
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88 lines
3.3 KiB
LLVM
88 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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define <4 x i32> @mulByZero(<4 x i16> %x) nounwind readnone ssp {
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; CHECK-LABEL: define <4 x i32> @mulByZero(
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; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: ret <4 x i32> zeroinitializer
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;
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
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ret <4 x i32> %a
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}
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define <4 x i32> @mulByOne(<4 x i16> %x) nounwind readnone ssp {
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; CHECK-LABEL: define <4 x i32> @mulByOne(
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; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[A:%.*]] = sext <4 x i16> [[X]] to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> [[A]]
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;
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %a
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}
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define <4 x i32> @constantMul() nounwind readnone ssp {
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; CHECK-LABEL: define <4 x i32> @constantMul(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: ret <4 x i32> splat (i32 6)
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;
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
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ret <4 x i32> %a
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}
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define <4 x i32> @constantMulS() nounwind readnone ssp {
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; CHECK-LABEL: define <4 x i32> @constantMulS(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: ret <4 x i32> splat (i32 -1)
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;
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entry:
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%b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %b
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}
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define <4 x i32> @constantMulU() nounwind readnone ssp {
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; CHECK-LABEL: define <4 x i32> @constantMulU(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: ret <4 x i32> splat (i32 65535)
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;
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entry:
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%b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %b
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}
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define <4 x i32> @complex1(<4 x i16> %x) nounwind readnone ssp {
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; CHECK-LABEL: define <4 x i32> @complex1(
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; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[A:%.*]] = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> splat (i16 2), <4 x i16> [[X]]) #[[ATTR2:[0-9]+]]
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; CHECK-NEXT: ret <4 x i32> [[A]]
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;
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
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%b = add <4 x i32> zeroinitializer, %a
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ret <4 x i32> %b
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}
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define <4 x i32> @complex2(<4 x i32> %x) nounwind readnone ssp {
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; CHECK-LABEL: define <4 x i32> @complex2(
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; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[B:%.*]] = add <4 x i32> [[X]], splat (i32 6)
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; CHECK-NEXT: ret <4 x i32> [[B]]
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;
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
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%b = add <4 x i32> %x, %a
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ret <4 x i32> %b
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}
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declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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