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TheRock/compiler/amd-llvm/llvm/test/Transforms/InstCombine/binop-select.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

1353 lines
42 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals smart
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
declare void @use(i32)
declare void @use_f32(float)
declare void @use_v2f16(<2 x half>)
declare void @use_v2i8(<2 x i8>)
declare i32 @llvm.sadd.sat.i32(i32, i32)
declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
define i32 @test1(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[Y:%.*]]
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]
; CHECK-NEXT: ret i32 [[ADD]]
;
%sub = sub i32 0, %x
%cond = select i1 %c, i32 %sub, i32 %y
%add = add i32 %cond, %x
ret i32 %add
}
define i32 @test2(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[X]]
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]
; CHECK-NEXT: ret i32 [[ADD]]
;
%sub = sub i32 0, %x
%cond = select i1 %c, i32 %sub, i32 %x
%add = add i32 %cond, %x
ret i32 %add
}
define i32 @test3(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 1
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[COND]], [[X]]
; CHECK-NEXT: ret i32 [[MUL]]
;
%sub = sub i32 0, %x
%cond = select i1 %c, i32 %sub, i32 1
%mul = mul i32 %cond, %x
ret i32 %mul
}
define i32 @test4(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 1
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[COND]], [[X]]
; CHECK-NEXT: ret i32 [[MUL]]
;
%sub = sub i32 0, %x
%cond = select i1 %c, i32 %sub, i32 1
%mul = mul i32 %cond, %x
ret i32 %mul
}
define i32 @test5(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[X:%.*]], i32 0
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]
; CHECK-NEXT: ret i32 [[ADD]]
;
%cond = select i1 %c, i32 %x, i32 0
%add = add i32 %cond, %x
ret i32 %add
}
define i32 @test_sub_deduce_true(i32 %x, i32 %y) {
; CHECK-LABEL: @test_sub_deduce_true(
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 9
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[X]], i32 [[Y:%.*]])
; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i32 15, i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[SUB]]
;
%c = icmp eq i32 %x, 9
%cond = select i1 %c, i32 6, i32 %y
%sub = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %cond)
ret i32 %sub
}
define i32 @test_sub_deduce_true_no_const_fold(i32 %x, i32 %y) {
; CHECK-LABEL: @test_sub_deduce_true_no_const_fold(
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 9
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C]], i32 [[Y:%.*]], i32 6
; CHECK-NEXT: [[SUB:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[X]], i32 [[COND]])
; CHECK-NEXT: ret i32 [[SUB]]
;
%c = icmp eq i32 %x, 9
%cond = select i1 %c, i32 %y, i32 6
%sub = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %cond)
ret i32 %sub
}
define i32 @test_sub_deduce_false(i32 %x, i32 %y) {
; CHECK-LABEL: @test_sub_deduce_false(
; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq i32 [[X:%.*]], 9
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[X]], i32 [[Y:%.*]])
; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C_NOT]], i32 16, i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[SUB]]
;
%c = icmp ne i32 %x, 9
%cond = select i1 %c, i32 %y, i32 7
%sub = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %cond)
ret i32 %sub
}
define <2 x i8> @test_sub_dont_deduce_with_undef_cond_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @test_sub_dont_deduce_with_undef_cond_vec(
; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 9, i8 undef>
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[C_NOT]], <2 x i8> splat (i8 7), <2 x i8> [[Y:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[X]], <2 x i8> [[COND]])
; CHECK-NEXT: ret <2 x i8> [[SUB]]
;
%c = icmp ne <2 x i8> %x, <i8 9, i8 undef>
%cond = select <2 x i1> %c, <2 x i8> %y, <2 x i8> <i8 7, i8 7>
%sub = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %cond)
ret <2 x i8> %sub
}
define <2 x i8> @test_sub_dont_deduce_with_poison_cond_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @test_sub_dont_deduce_with_poison_cond_vec(
; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 poison, i8 9>
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[C_NOT]], <2 x i8> splat (i8 7), <2 x i8> [[Y:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[X]], <2 x i8> [[COND]])
; CHECK-NEXT: ret <2 x i8> [[SUB]]
;
%c = icmp ne <2 x i8> %x, <i8 poison, i8 9>
%cond = select <2 x i1> %c, <2 x i8> %y, <2 x i8> <i8 7, i8 7>
%sub = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %cond)
ret <2 x i8> %sub
}
define <2 x i8> @test_sub_deduce_with_undef_val_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @test_sub_deduce_with_undef_val_vec(
; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 1, i8 2>
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[X]], <2 x i8> [[Y:%.*]])
; CHECK-NEXT: [[SUB:%.*]] = select <2 x i1> [[C_NOT]], <2 x i8> <i8 4, i8 -1>, <2 x i8> [[TMP1]]
; CHECK-NEXT: ret <2 x i8> [[SUB]]
;
%c = icmp ne <2 x i8> %x, <i8 1, i8 2>
%cond = select <2 x i1> %c, <2 x i8> %y, <2 x i8> <i8 3, i8 undef>
%sub = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %cond)
ret <2 x i8> %sub
}
define i32 @test6(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test6(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[X:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i32 [[COND]], [[X]]
; CHECK-NEXT: ret i32 [[AND]]
;
%cond = select i1 %c, i32 7, i32 %x
%and = and i32 %cond, %x
ret i32 %and
}
define i32 @test7(i1 %c, i32 %x) {
; CHECK-LABEL: @test7(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[X]], i32 [[SUB]]
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X]], [[COND]]
; CHECK-NEXT: ret i32 [[DIV]]
;
%sub = sub i32 0, %x
%cond = select i1 %c, i32 %x, i32 %sub
%div = sdiv i32 %x, %cond
ret i32 %div
}
define i32 @test8(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 42, [[COND]]
; CHECK-NEXT: ret i32 [[DIV]]
;
%cond = select i1 %c, i32 7, i32 %y
%div = sdiv i32 42, %cond
ret i32 %div
}
define i32 @test9(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test9(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 1, i32 [[X:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB]]
;
%cond = select i1 %c, i32 1, i32 %x
%sub = sub nsw i32 0, %cond
ret i32 %sub
}
define i32 @test10(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test10(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 42, [[COND]]
; CHECK-NEXT: ret i32 [[DIV]]
;
%cond = select i1 %c, i32 7, i32 %y
%div = udiv i32 42, %cond
ret i32 %div
}
define i32 @test11(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
; CHECK-NEXT: [[DIV:%.*]] = srem i32 42, [[COND]]
; CHECK-NEXT: ret i32 [[DIV]]
;
%cond = select i1 %c, i32 7, i32 %y
%div = srem i32 42, %cond
ret i32 %div
}
define i32 @test12(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @test12(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
; CHECK-NEXT: [[DIV:%.*]] = urem i32 42, [[COND]]
; CHECK-NEXT: ret i32 [[DIV]]
;
%cond = select i1 %c, i32 7, i32 %y
%div = urem i32 42, %cond
ret i32 %div
}
define i32 @extra_use(i1 %c, i32 %x, i32 %y) {
; CHECK-LABEL: @extra_use(
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 1, i32 [[X:%.*]]
; CHECK-NEXT: tail call void @use(i32 [[COND]])
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB]]
;
%cond = select i1 %c, i32 1, i32 %x
tail call void @use(i32 %cond)
%sub = sub nsw i32 0, %cond
ret i32 %sub
}
define i32 @extra_use2(i1 %c, i32 %x) {
; CHECK-LABEL: @extra_use2(
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[X]], i32 [[SUB]]
; CHECK-NEXT: tail call void @use(i32 [[COND]])
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[COND]], [[X]]
; CHECK-NEXT: ret i32 [[DIV]]
;
%sub = sub i32 0, %x
%cond = select i1 %c, i32 %x, i32 %sub
tail call void @use(i32 %cond)
%div = sdiv i32 %cond, %x
ret i32 %div
}
define i32 @and_sel_op0(i1 %b) {
; CHECK-LABEL: @and_sel_op0(
; CHECK-NEXT: [[S:%.*]] = zext i1 [[B:%.*]] to i32
; CHECK-NEXT: ret i32 [[S]]
;
%s = select i1 %b, i32 25, i32 0
%r = and i32 %s, 1
ret i32 %r
}
define i32 @and_sel_op0_use(i1 %b) {
; CHECK-LABEL: @and_sel_op0_use(
; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 25, i32 0
; CHECK-NEXT: call void @use(i32 [[S]])
; CHECK-NEXT: [[R:%.*]] = and i32 [[S]], 1
; CHECK-NEXT: ret i32 [[R]]
;
%s = select i1 %b, i32 25, i32 0
call void @use(i32 %s)
%r = and i32 %s, 1
ret i32 %r
}
define i32 @mul_sel_op0(i1 %b, i32 %x) {
; CHECK-LABEL: @mul_sel_op0(
; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i32 0, i32 42
; CHECK-NEXT: ret i32 [[R]]
;
%d = udiv exact i32 42, %x
%s = select i1 %b, i32 0, i32 %d
%r = mul i32 %s, %x
ret i32 %r
}
define i32 @mul_sel_op0_use(i1 %b, i32 %x) {
; CHECK-LABEL: @mul_sel_op0_use(
; CHECK-NEXT: [[D:%.*]] = udiv exact i32 42, [[X:%.*]]
; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 0, i32 [[D]]
; CHECK-NEXT: call void @use(i32 [[S]])
; CHECK-NEXT: [[R:%.*]] = mul i32 [[S]], [[X]]
; CHECK-NEXT: ret i32 [[R]]
;
%d = udiv exact i32 42, %x
%s = select i1 %b, i32 0, i32 %d
call void @use(i32 %s)
%r = mul i32 %s, %x
ret i32 %r
}
define i32 @sub_sel_op1(i1 %b) {
; CHECK-LABEL: @sub_sel_op1(
; CHECK-NEXT: [[NOT_B:%.*]] = xor i1 [[B:%.*]], true
; CHECK-NEXT: [[R:%.*]] = zext i1 [[NOT_B]] to i32
; CHECK-NEXT: ret i32 [[R]]
;
%s = select i1 %b, i32 42, i32 41
%r = sub nsw i32 42, %s
ret i32 %r
}
define i32 @sub_sel_op1_use(i1 %b) {
; CHECK-LABEL: @sub_sel_op1_use(
; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 42, i32 41
; CHECK-NEXT: call void @use(i32 [[S]])
; CHECK-NEXT: [[R:%.*]] = sub nuw nsw i32 42, [[S]]
; CHECK-NEXT: ret i32 [[R]]
;
%s = select i1 %b, i32 42, i32 41
call void @use(i32 %s)
%r = sub nuw nsw i32 42, %s
ret i32 %r
}
define float @fadd_sel_op0(i1 %b, float %x) {
; CHECK-LABEL: @fadd_sel_op0(
; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], float -inf, float +inf
; CHECK-NEXT: ret float [[R]]
;
%s = select i1 %b, float 0xFFF0000000000000, float 0x7FF0000000000000
%r = fadd nnan float %s, %x
ret float %r
}
define float @fadd_sel_op0_use(i1 %b, float %x) {
; CHECK-LABEL: @fadd_sel_op0_use(
; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], float -inf, float +inf
; CHECK-NEXT: call void @use_f32(float [[S]])
; CHECK-NEXT: [[R:%.*]] = fadd nnan float [[S]], [[X:%.*]]
; CHECK-NEXT: ret float [[R]]
;
%s = select i1 %b, float 0xFFF0000000000000, float 0x7FF0000000000000
call void @use_f32(float %s)
%r = fadd nnan float %s, %x
ret float %r
}
define <2 x half> @fmul_sel_op1(i1 %b, <2 x half> %p) {
; CHECK-LABEL: @fmul_sel_op1(
; CHECK-NEXT: ret <2 x half> zeroinitializer
;
%x = fadd <2 x half> %p, <half 1.0, half 2.0> ; thwart complexity-based canonicalization
%s = select i1 %b, <2 x half> zeroinitializer, <2 x half> <half 0xHffff, half 0xHffff>
%r = fmul nnan nsz <2 x half> %x, %s
ret <2 x half> %r
}
define <2 x half> @fmul_sel_op1_use(i1 %b, <2 x half> %p) {
; CHECK-LABEL: @fmul_sel_op1_use(
; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], <2 x half> zeroinitializer, <2 x half> splat (half -nan(0x1FF))
; CHECK-NEXT: call void @use_v2f16(<2 x half> [[S]])
; CHECK-NEXT: ret <2 x half> zeroinitializer
;
%x = fadd <2 x half> %p, <half 1.0, half 2.0> ; thwart complexity-based canonicalization
%s = select i1 %b, <2 x half> zeroinitializer, <2 x half> <half 0xHffff, half 0xHffff>
call void @use_v2f16(<2 x half> %s)
%r = fmul nnan nsz <2 x half> %x, %s
ret <2 x half> %r
}
define i32 @ashr_sel_op1(i1 %b) {
; CHECK-LABEL: @ashr_sel_op1(
; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i32 -1, i32 -2
; CHECK-NEXT: ret i32 [[R]]
;
%s = select i1 %b, i32 2, i32 0
%r = ashr i32 -2, %s
ret i32 %r
}
define i32 @ashr_sel_op1_use(i1 %b) {
; CHECK-LABEL: @ashr_sel_op1_use(
; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 2, i32 0
; CHECK-NEXT: call void @use(i32 [[S]])
; CHECK-NEXT: [[R:%.*]] = ashr i32 -2, [[S]]
; CHECK-NEXT: ret i32 [[R]]
;
%s = select i1 %b, i32 2, i32 0
call void @use(i32 %s)
%r = ashr i32 -2, %s
ret i32 %r
}
define i8 @commonArgWithOr0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithOr0(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 24
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 0, i8 8
%v2 = or i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithOr1(i1 %arg0) {
; CHECK-LABEL: @commonArgWithOr1(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 23
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 1, i8 7
%v2 = or i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithOr2(i1 %arg0) {
; CHECK-LABEL: @commonArgWithOr2(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 21, i8 58
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 42
%v2 = or i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithAnd0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd0(
; CHECK-NEXT: ret i8 16
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 0, i8 8
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithAnd1(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd1(
; CHECK-NEXT: ret i8 16
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 8, i8 1
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithAnd2(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd2(
; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 1, i8 7
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithAnd3(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd3(
; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 42
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithXor0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor0(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 24
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 0, i8 8
%v2 = xor i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithXor1(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor1(
; CHECK-NEXT: [[V2:%.*]] = select i1 [[ARG0:%.*]], i8 8, i8 1
; CHECK-NEXT: ret i8 [[V2]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 9, i8 1
%v2 = xor i8 %v1, %v0
ret i8 %v2
}
define i8 @commonArgWithXor2(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor2(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 16, i8 23
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 1, i8 7
%v2 = xor i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithXor3(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor3(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 20, i8 61
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 45
%v2 = xor i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i8 @commonArgWithAdd0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAdd0(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 22, i8 61
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 45
%v2 = add i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}
define i32 @OrSelectIcmpZero(i32 %a, i32 %b) {
; CHECK-LABEL: @OrSelectIcmpZero(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0
; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 [[A]]
; CHECK-NEXT: ret i32 [[OR]]
;
%cmp = icmp eq i32 %a, 0
%sel = select i1 %cmp, i32 %b, i32 0
%or = or i32 %sel, %a
ret i32 %or
}
define i32 @OrSelectIcmpNonZero(i32 %a, i32 %b) {
; CHECK-LABEL: @OrSelectIcmpNonZero(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 42
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL]], [[A]]
; CHECK-NEXT: ret i32 [[OR]]
;
%cmp = icmp eq i32 %a, 0
%sel = select i1 %cmp, i32 %b, i32 42
%or = or i32 %sel, %a
ret i32 %or
}
define i8 @BinOpSelectBinOpMultiUseRegsWithSelect1(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
; CHECK-NEXT: [[USE:%.*]] = add i8 [[V1]], 42
; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[USE]], i8 [[V3]]
; CHECK-NEXT: ret i8 [[RETVAL]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 4, %arg0
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 1, %v2
%use = add i8 %v1, 42
%retVal = select i1 %whatToReturn, i8 %use, i8 %v3
ret i8 %retVal
}
define i8 @BinOpSelectBinOpMultiUseRegsWithSelect2(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
; CHECK-NEXT: [[USE:%.*]] = add i8 [[V2]], 42
; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[USE]], i8 [[V3]]
; CHECK-NEXT: ret i8 [[RETVAL]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 4, %arg0
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 1, %v2
%use = add i8 %v2, 42
%retVal = select i1 %whatToReturn, i8 %use, i8 %v3
ret i8 %retVal
}
define i8 @BinOpSelectBinOpMultiUseRegsWithSelect3(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect3(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[V1]], i8 [[V3]]
; CHECK-NEXT: ret i8 [[RETVAL]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 4, %arg0
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 1, %v2
%retVal = select i1 %whatToReturn, i8 %v1, i8 %v3
ret i8 %retVal
}
define i8 @BinOpSelectBinOpMultiUseRegsWithSelect4(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect4(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[NOT_WHATTORETURN:%.*]] = xor i1 [[WHATTORETURN:%.*]], true
; CHECK-NEXT: [[V3:%.*]] = zext i1 [[NOT_WHATTORETURN]] to i8
; CHECK-NEXT: [[RETVAL:%.*]] = or i8 [[V2]], [[V3]]
; CHECK-NEXT: ret i8 [[RETVAL]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 4, %arg0
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 1, %v2
%retVal = select i1 %whatToReturn, i8 %v2, i8 %v3
ret i8 %retVal
}
; or tests
define i8 @orSelectOrNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 1
ret i8 %v3
}
define i8 @orSelectOrNoCommonBits2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrNoCommonBits2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = zext i1 [[V0]] to i8
; CHECK-NEXT: [[V2:%.*]] = or i8 [[ARG0:%.*]], [[V1]]
; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 4
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 1
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 4
ret i8 %v3
}
define i8 @orSelectOrReserved(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrReserved(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 13, i8 15
; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 11
%v2 = select i1 %v0, i8 %arg0, i8 %v1
%v3 = or i8 %v2, 13
ret i8 %v3
}
define i8 @orSelectOrSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 13
; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 13
ret i8 %v3
}
define i8 @orSelectOrSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 11
; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 13
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 11
ret i8 %v3
}
define i8 @orSelectOrSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 5
; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 5
ret i8 %v3
}
define i8 @orSelectOrSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 11
; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 5
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 11
ret i8 %v3
}
define i8 @orSelectOrSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSame(
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 42
; CHECK-NEXT: ret i8 [[V1]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 42
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 42
ret i8 %v3
}
; and tests
define i8 @andSelectandNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @andSelectandNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[ARG0:%.*]], 1
; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 0, i8 [[TMP1]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = and i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = and i8 %v2, 1
ret i8 %v3
}
define i8 @andSelectandNoCommonBits2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @andSelectandNoCommonBits2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V3:%.*]] = and i8 [[V2:%.*]], 4
; CHECK-NEXT: [[V4:%.*]] = select i1 [[V0]], i8 0, i8 [[V3]]
; CHECK-NEXT: ret i8 [[V4]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = and i8 %arg0, 1
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = and i8 %v2, 4
ret i8 %v3
}
define i8 @andSelectandSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @andSelectandSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 9, i8 13
; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = and i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = and i8 %v2, 13
ret i8 %v3
}
define i8 @andSelectandSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @andSelectandSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 9, i8 11
; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = and i8 %arg0, 13
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = and i8 %v2, 11
ret i8 %v3
}
define i8 @andSelectandSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @andSelectandSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 1, i8 5
; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = and i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = and i8 %v2, 5
ret i8 %v3
}
define i8 @andSelectandSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @andSelectandSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 1, i8 11
; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = and i8 %arg0, 5
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = and i8 %v2, 11
ret i8 %v3
}
define i8 @andSelectandSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @andSelectandSame(
; CHECK-NEXT: [[V1:%.*]] = and i8 [[ARG0:%.*]], 42
; CHECK-NEXT: ret i8 [[V1]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = and i8 %arg0, 42
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = and i8 %v2, 42
ret i8 %v3
}
; xor tests
define i8 @xorSelectxorNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = xor i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = xor i8 %v2, 1
ret i8 %v3
}
define i8 @xorSelectxorNoCommonBits2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorNoCommonBits2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = zext i1 [[V0]] to i8
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[ARG0:%.*]], [[V1]]
; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 4
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = xor i8 %arg0, 1
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = xor i8 %v2, 4
ret i8 %v3
}
define i8 @xorSelectxorSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 6, i8 13
; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = xor i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = xor i8 %v2, 13
ret i8 %v3
}
define i8 @xorSelectxorSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 6, i8 11
; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = xor i8 %arg0, 13
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = xor i8 %v2, 11
ret i8 %v3
}
define i8 @xorSelectxorSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 14, i8 5
; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = xor i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = xor i8 %v2, 5
ret i8 %v3
}
define i8 @xorSelectxorSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 14, i8 11
; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = xor i8 %arg0, 5
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = xor i8 %v2, 11
ret i8 %v3
}
define i8 @xorSelectxorSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSame(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 42
; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 [[ARG0]], i8 [[V1]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = xor i8 %arg0, 42
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = xor i8 %v2, 42
ret i8 %v3
}
; add tests
define i8 @addSelectaddNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1, !prof [[PROF0:![0-9]+]]
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = add i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0, !prof !0
%v3 = add i8 %v2, 1
ret i8 %v3
}
define i8 @addSelectaddNoCommonBits2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddNoCommonBits2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = zext i1 [[V0]] to i8
; CHECK-NEXT: [[V2:%.*]] = add i8 [[ARG0:%.*]], [[V1]]
; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 4
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = add i8 %arg0, 1
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = add i8 %v2, 4
ret i8 %v3
}
define i8 @addSelectaddSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 24, i8 13
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = add i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = add i8 %v2, 13
ret i8 %v3
}
define i8 @addSelectaddSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 24, i8 11
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = add i8 %arg0, 13
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = add i8 %v2, 11
ret i8 %v3
}
define i8 @addSelectaddSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 16, i8 5
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = add i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = add i8 %v2, 5
ret i8 %v3
}
define i8 @addSelectaddSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 16, i8 11
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = add i8 %arg0, 5
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = add i8 %v2, 11
ret i8 %v3
}
define i8 @addSelectaddSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSame(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 84, i8 42, !prof [[PROF0]]
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = add i8 %arg0, 42
%v2 = select i1 %v0, i8 %v1, i8 %arg0, !prof !0
%v3 = add i8 %v2, 42
ret i8 %v3
}
!0 = !{!"branch_weights", i32 10, i32 90}
; sub tests
define i8 @subSelectsubNoCommonBitsConstOnLeft1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubNoCommonBitsConstOnLeft1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = sub i8 4, [[ARG0:%.*]]
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -1
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 4, %arg0
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 1
ret i8 %v3
}
define i8 @subSelectsubNoCommonBitsConstOnLeft2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubNoCommonBitsConstOnLeft2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -4
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V3:%.*]] = sub i8 1, [[V2]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 1, %v2
ret i8 %v3
}
define i8 @subSelectsubNoCommonBitsConstOnLeft3(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubNoCommonBitsConstOnLeft3(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 4, [[TMP2:%.*]]
; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 [[TMP1]], i8 [[TMP2]]
; CHECK-NEXT: [[V4:%.*]] = sub i8 1, [[V3]]
; CHECK-NEXT: ret i8 [[V4]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 4, %arg0
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 1, %v2
ret i8 %v3
}
define i8 @subSelectsubNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -5, i8 -1
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 1
ret i8 %v3
}
define i8 @subSelectsubNoCommonBits2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubNoCommonBits2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = sext i1 [[V0]] to i8
; CHECK-NEXT: [[V2:%.*]] = add i8 [[ARG0:%.*]], [[V1]]
; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -4
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 1
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 4
ret i8 %v3
}
define i8 @subSelectsubSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -24, i8 -13
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 13
ret i8 %v3
}
define i8 @subSelectsubSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -24, i8 -11
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 13
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 11
ret i8 %v3
}
define i8 @subSelectsubSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -16, i8 -5
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 5
ret i8 %v3
}
define i8 @subSelectsubSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -16, i8 -11
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 5
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 11
ret i8 %v3
}
define i8 @subSelectsubSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSame(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -84, i8 -42
; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = sub i8 %arg0, 42
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = sub i8 %v2, 42
ret i8 %v3
}
; mul tests
define i8 @mulSelectmulNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = shl i8 [[ARG0:%.*]], 2
; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V2:%.*]] = shl i8 [[V3]], 1
; CHECK-NEXT: ret i8 [[V2]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = mul i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = mul i8 %v2, 2
ret i8 %v3
}
define i8 @mulSelectmulNoCommonBits2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulNoCommonBits2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG2:%.*]], 3
; CHECK-NEXT: [[ARG0:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG2]]
; CHECK-NEXT: [[V3:%.*]] = shl i8 [[ARG0]], 2
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = mul i8 %arg0, 3
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = mul i8 %v2, 4
ret i8 %v3
}
define i8 @mulSelectmulmulset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulmulset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -113, i8 13
; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = mul i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = mul i8 %v2, 13
ret i8 %v3
}
define i8 @mulSelectmulmulset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulmulset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -113, i8 11
; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = mul i8 %arg0, 13
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = mul i8 %v2, 11
ret i8 %v3
}
define i8 @mulSelectmulSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 55, i8 5
; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = mul i8 %arg0, 11
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = mul i8 %v2, 5
ret i8 %v3
}
define i8 @mulSelectmulSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 55, i8 11
; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = mul i8 %arg0, 5
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = mul i8 %v2, 11
ret i8 %v3
}
define i8 @mulSelectmulSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulSame(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -28, i8 42
; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = mul i8 %arg0, 42
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = mul i8 %v2, 42
ret i8 %v3
}
define i8 @orSelectOrUses(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrUses(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
; CHECK-NEXT: [[RES:%.*]] = add i8 [[V1]], [[V3]]
; CHECK-NEXT: ret i8 [[RES]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or i8 %arg0, 4
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = or i8 %v2, 1
%res = add i8 %v1, %v3
ret i8 %res
}
define i8 @udivSelectudivSomeCommon1InfLoopRep(i8 %arg0, i8 %arg1, i1 %v0) {
; CHECK-LABEL: @udivSelectudivSomeCommon1InfLoopRep(
; CHECK-NEXT: [[V1:%.*]] = udiv i8 11, [[ARG0:%.*]]
; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0:%.*]], i8 [[V1]], i8 [[ARG0]]
; CHECK-NEXT: [[V3:%.*]] = udiv i8 [[V2]], 5
; CHECK-NEXT: ret i8 [[V3]]
;
%v01 = icmp sgt i8 %arg0, 0
%v1 = udiv i8 11, %arg0
%v2 = select i1 %v0, i8 %v1, i8 %arg0
%v3 = udiv i8 %v2, 5
ret i8 %v3
}
; vector tests
define <4 x i8> @orSelectOrVectors(<4 x i8> %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrVectors(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], <4 x i8> <i8 5, i8 6, i8 27, i8 21>, <4 x i8> <i8 1, i8 4, i8 17, i8 5>
; CHECK-NEXT: [[V3:%.*]] = or <4 x i8> [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret <4 x i8> [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
%v1 = or <4 x i8> %arg0, <i8 4, i8 2, i8 11, i8 21>
%v2 = select i1 %v0, <4 x i8> %v1, <4 x i8> %arg0
%v3 = or <4 x i8> %v2, <i8 1, i8 4, i8 17, i8 5>
ret <4 x i8> %v3
}
;.
; CHECK: [[PROF0]] = !{!"branch_weights", i32 10, i32 90}
;.
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