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166 lines
4.7 KiB
LLVM
166 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=instcombine -S < %s | FileCheck %s
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define i64 @test_or(i64 %a) {
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; CHECK-LABEL: @test_or(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = or i64 [[A:%.*]], 15
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: tail call void @use(i64 [[TMP0]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%iv.next = or i64 %iv, 15
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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define i64 @test_or2(i64 %a, i64 %b) {
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; CHECK-LABEL: @test_or2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[IV_NEXT:%.*]] = or i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%iv.next = or i64 %iv, %b
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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define i64 @test_or3(i64 %a, i64 %b) {
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; CHECK-LABEL: @test_or3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[IV_NEXT:%.*]] = or i64 [[B:%.*]], [[A:%.*]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%iv.next = or i64 %b, %iv
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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define i64 @test_or4(i64 %a, ptr %p) {
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; CHECK-LABEL: @test_or4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[A:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[STEP:%.*]] = load volatile i64, ptr [[P:%.*]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = or i64 [[IV]], [[STEP]]
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; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%step = load volatile i64, ptr %p
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%iv.next = or i64 %iv, %step
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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define i64 @test_and(i64 %a) {
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; CHECK-LABEL: @test_and(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[A:%.*]], 15
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: tail call void @use(i64 [[TMP0]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%iv.next = and i64 %iv, 15
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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define i64 @test_and2(i64 %a, i64 %b) {
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; CHECK-LABEL: @test_and2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[IV_NEXT:%.*]] = and i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%iv.next = and i64 %iv, %b
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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define i64 @test_and3(i64 %a, i64 %b) {
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; CHECK-LABEL: @test_and3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[IV_NEXT:%.*]] = and i64 [[B:%.*]], [[A:%.*]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%iv.next = and i64 %b, %iv
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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define i64 @test_and4(i64 %a, ptr %p) {
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; CHECK-LABEL: @test_and4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[A:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[STEP:%.*]] = load volatile i64, ptr [[P:%.*]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = and i64 [[IV]], [[STEP]]
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; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ]
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%step = load volatile i64, ptr %p
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%iv.next = and i64 %iv, %step
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tail call void @use(i64 %iv.next)
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br label %loop
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}
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declare void @use(i64)
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