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TheRock/compiler/amd-llvm/llvm/test/Transforms/InstSimplify/ConstProp/active-lane-mask.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

382 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=instsimplify -S -o - %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
@glob = external global i32
define <16 x i1> @v16i1_0() {
; CHECK-LABEL: @v16i1_0(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> zeroinitializer
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 0)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_1() {
; CHECK-LABEL: @v16i1_1(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 1)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_8() {
; CHECK-LABEL: @v16i1_8(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 8)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_15() {
; CHECK-LABEL: @v16i1_15(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 15)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_16() {
; CHECK-LABEL: @v16i1_16(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> splat (i1 true)
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 16)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_100() {
; CHECK-LABEL: @v16i1_100(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> splat (i1 true)
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 100)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_m1() {
; CHECK-LABEL: @v16i1_m1(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> splat (i1 true)
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 -1)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_10_11() {
; CHECK-LABEL: @v16i1_10_11(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 10, i32 11)
ret <16 x i1> %int
}
define <16 x i1> @v16i1_12_11() {
; CHECK-LABEL: @v16i1_12_11(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <16 x i1> zeroinitializer
;
entry:
%int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 12, i32 11)
ret <16 x i1> %int
}
define <8 x i1> @v8i1_0() {
; CHECK-LABEL: @v8i1_0(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> zeroinitializer
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 0)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_1() {
; CHECK-LABEL: @v8i1_1(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 1)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_4() {
; CHECK-LABEL: @v8i1_4(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 4)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_7() {
; CHECK-LABEL: @v8i1_7(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 7)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_8() {
; CHECK-LABEL: @v8i1_8(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> splat (i1 true)
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 8)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_100() {
; CHECK-LABEL: @v8i1_100(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> splat (i1 true)
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 100)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_m1() {
; CHECK-LABEL: @v8i1_m1(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> splat (i1 true)
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 -1)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_10_11() {
; CHECK-LABEL: @v8i1_10_11(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 10, i32 11)
ret <8 x i1> %int
}
define <8 x i1> @v8i1_12_11() {
; CHECK-LABEL: @v8i1_12_11(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <8 x i1> zeroinitializer
;
entry:
%int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 12, i32 11)
ret <8 x i1> %int
}
define <4 x i1> @v4i1_0() {
; CHECK-LABEL: @v4i1_0(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> zeroinitializer
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 0)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_1() {
; CHECK-LABEL: @v4i1_1(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> <i1 true, i1 false, i1 false, i1 false>
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 1)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_3() {
; CHECK-LABEL: @v4i1_3(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 false>
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 3)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_4() {
; CHECK-LABEL: @v4i1_4(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> splat (i1 true)
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 4)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_100() {
; CHECK-LABEL: @v4i1_100(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> splat (i1 true)
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 100)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_m1() {
; CHECK-LABEL: @v4i1_m1(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> splat (i1 true)
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 -1)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_10_11() {
; CHECK-LABEL: @v4i1_10_11(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> <i1 true, i1 false, i1 false, i1 false>
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 10, i32 11)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_12_11() {
; CHECK-LABEL: @v4i1_12_11(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <4 x i1> zeroinitializer
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 12, i32 11)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_nc1(i32 %x) {
; CHECK-LABEL: @v4i1_nc1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INT:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[X:%.*]], i32 11)
; CHECK-NEXT: ret <4 x i1> [[INT]]
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %x, i32 11)
ret <4 x i1> %int
}
define <4 x i1> @v4i1_nc2(i32 %x) {
; CHECK-LABEL: @v4i1_nc2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INT:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 11, i32 [[X:%.*]])
; CHECK-NEXT: ret <4 x i1> [[INT]]
;
entry:
%int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 11, i32 %x)
ret <4 x i1> %int
}
define <4 x float> @poisonc(<4 x float> %a, i32 %n) {
; CHECK-LABEL: @poisonc(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VAR27:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 poison, i32 1024)
; CHECK-NEXT: [[VAR33:%.*]] = select <4 x i1> [[VAR27]], <4 x float> [[A:%.*]], <4 x float> zeroinitializer
; CHECK-NEXT: ret <4 x float> [[VAR33]]
;
entry:
%new0 = shl i1 0, 1
%last = zext i1 %new0 to i32
%var27 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %last, i32 1024)
%var33 = select <4 x i1> %var27, <4 x float> %a, <4 x float> zeroinitializer
ret <4 x float> %var33
}
define <vscale x 4 x i1> @nxv4i1_12_12() {
; CHECK-LABEL: @nxv4i1_12_12(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer
;
entry:
%mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 12, i32 12)
ret <vscale x 4 x i1> %mask
}
define <vscale x 4 x i1> @nxv4i1_8_4() {
; CHECK-LABEL: @nxv4i1_8_4(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer
;
entry:
%mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 8, i32 4)
ret <vscale x 4 x i1> %mask
}
define <vscale x 16 x i1> @nxv16i1_0_0() {
; CHECK-LABEL: @nxv16i1_0_0(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer
;
entry:
%mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 0)
ret <vscale x 16 x i1> %mask
}
define <vscale x 16 x i1> @nxv16i1_0_constexpr() {
; CHECK-LABEL: @nxv16i1_0_constexpr(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 ptrtoint (ptr @glob to i64))
; CHECK-NEXT: ret <vscale x 16 x i1> [[MASK]]
;
entry:
%mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 ptrtoint (ptr @glob to i64))
ret <vscale x 16 x i1> %mask
}
define <vscale x 16 x i1> @nxv16i1_constexpr_0() {
; CHECK-LABEL: @nxv16i1_constexpr_0(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer
;
entry:
%mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 ptrtoint (ptr @glob to i64), i64 0)
ret <vscale x 16 x i1> %mask
}
define <vscale x 16 x i1> @nxv16i1_constexpr_constexpr() {
; CHECK-LABEL: @nxv16i1_constexpr_constexpr(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 ptrtoint (ptr @glob to i64), i64 ptrtoint (ptr getelementptr inbounds nuw (i8, ptr @glob, i64 2) to i64))
; CHECK-NEXT: ret <vscale x 16 x i1> [[MASK]]
;
entry:
%mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 ptrtoint (ptr @glob to i64), i64 ptrtoint (ptr getelementptr inbounds nuw (i8, ptr @glob, i64 2) to i64))
ret <vscale x 16 x i1> %mask
}
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32, i32)
declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64, i64)
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