derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
1a182e2dac58879f215c0fad0f5f78c76dcafe56
TheRock/compiler/amd-llvm/llvm/test/Transforms/LICM/hoist-add-sub.ll
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

1150 lines
42 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -passes=licm -verify-memoryssa < %s | FileCheck %s
; x - iv < 4 ==> iv > x - 4
define i32 @test_01(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_01
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nsw i32 [[X]], 4
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp sgt i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !0
%length = load i32, ptr %length_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nsw i32 %x, %iv
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
define i32 @test_01_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_01_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG1:![0-9]+]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG2:![0-9]+]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nuw i32 [[X]], 4
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ugt i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !2
%length = load i32, ptr %length_p, !range !1
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nuw i32 %x, %iv
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
; TODO: x - iv < 4 ==> iv > x - 4
define i32 @test_01a(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_01a
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp sge i32 [[X]], 0
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp sge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = sub nsw i32 [[X]], [[IV]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp sge i32 %x, 0
%precond_2 = icmp sge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nsw i32 %x, %iv
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
define i32 @test_01a_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_01a_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp uge i32 [[X]], 0
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp uge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = sub nuw i32 [[X]], [[IV]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp uge i32 %x, 0
%precond_2 = icmp uge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nuw i32 %x, %iv
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
; Range info is missing for x, cannot prove no-overflow. Should not hoist.
define i32 @test_01_neg(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_01_neg
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[ARITH:%.*]] = sub nsw i32 [[X]], [[IV]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nsw i32 %x, %iv
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
define i32 @test_01_neg_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_01_neg_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[ARITH:%.*]] = sub nuw i32 [[X]], [[IV]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nuw i32 %x, %iv
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
; x + iv < 4 ==> iv < 4 - x
define i32 @test_02(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_02
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nsw i32 4, [[X]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !0
%length = load i32, ptr %length_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nsw i32 %x, %iv
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
define i32 @test_02_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_02_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG3:![0-9]+]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG2]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nuw i32 4, [[X]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !3
%length = load i32, ptr %length_p, !range !1
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nuw i32 %x, %iv
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
; TODO: x + iv < 4 ==> iv < 4 - x
define i32 @test_02a(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_02a
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp sge i32 [[X]], 0
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp sge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = add nsw i32 [[X]], [[IV]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp sge i32 %x, 0
%precond_2 = icmp sge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nsw i32 %x, %iv
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
define i32 @test_02a_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_02a_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp uge i32 [[X]], 0
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp uge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = add nuw i32 [[X]], [[IV]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp uge i32 %x, 0
%precond_2 = icmp uge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nuw i32 %x, %iv
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
; iv - x < 4 ==> iv < 4 + x
define i32 @test_03(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_03
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG2]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = add nsw i32 [[X]], 4
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !1
%length = load i32, ptr %length_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nsw i32 %iv, %x
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
define i32 @test_03_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_03_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG2]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG2]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = add nuw i32 [[X]], 4
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !1
%length = load i32, ptr %length_p, !range !1
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nuw i32 %iv, %x
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
; TODO: iv - x < 4 ==> iv < 4 + x
define i32 @test_03a(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_03a
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp ult i32 [[X]], 2147483640
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp sge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = sub nsw i32 [[IV]], [[X]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp ult i32 %x, 2147483640
%precond_2 = icmp sge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nsw i32 %iv, %x
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
define i32 @test_03a_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_03a_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp ult i32 [[X]], 2147483640
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp uge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = sub nuw i32 [[IV]], [[X]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp ult i32 %x, 2147483640
%precond_2 = icmp uge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = sub nuw i32 %iv, %x
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
; iv + x < 4 ==> iv < 4 - x
define i32 @test_04(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_04
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nsw i32 4, [[X]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !0
%length = load i32, ptr %length_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nsw i32 %iv, %x
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
define i32 @test_04_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_04_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG3]]
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4, !range [[RNG2]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nuw i32 4, [[X]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
;
entry:
%x = load i32, ptr %x_p, !range !3
%length = load i32, ptr %length_p, !range !1
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nuw i32 %iv, %x
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
}
; TODO: iv + x < 4 ==> iv < 4 - x
define i32 @test_04a(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_04a
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp sge i32 [[X]], 0
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp sge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = add nsw i32 [[IV]], [[X]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp sge i32 %x, 0
%precond_2 = icmp sge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nsw i32 %iv, %x
%x_check = icmp slt i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
define i32 @test_04a_unsigned(ptr %p, ptr %x_p, ptr %length_p) {
; CHECK-LABEL: define i32 @test_04a_unsigned
; CHECK-SAME: (ptr [[P:%.*]], ptr [[X_P:%.*]], ptr [[LENGTH_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4
; CHECK-NEXT: [[LENGTH:%.*]] = load i32, ptr [[LENGTH_P]], align 4
; CHECK-NEXT: [[PRECOND_1:%.*]] = icmp sge i32 [[X]], 0
; CHECK-NEXT: [[PRECOND_2:%.*]] = icmp sge i32 [[LENGTH]], 0
; CHECK-NEXT: [[PRECOND:%.*]] = and i1 [[PRECOND_1]], [[PRECOND_2]]
; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[FAILED:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
; CHECK-NEXT: [[ARITH:%.*]] = add nuw i32 [[IV]], [[X]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[ARITH]], 4
; CHECK-NEXT: br i1 [[X_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], [[LENGTH]]
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; CHECK: out_of_bounds:
; CHECK-NEXT: ret i32 -1
; CHECK: failed:
; CHECK-NEXT: ret i32 -2
;
entry:
%x = load i32, ptr %x_p
%length = load i32, ptr %length_p
%precond_1 = icmp sge i32 %x, 0
%precond_2 = icmp sge i32 %length, 0
%precond = and i1 %precond_1, %precond_2
br i1 %precond, label %loop, label %failed
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = add nuw i32 %iv, %x
%x_check = icmp ult i32 %arith, 4
br i1 %x_check, label %out_of_bounds, label %backedge
backedge:
%el.ptr = getelementptr i32, ptr %p, i32 %iv
store i32 1, ptr %el.ptr
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, %length
br i1 %loop_cond, label %loop, label %exit
exit:
ret i32 %iv.next
out_of_bounds:
ret i32 -1
failed:
ret i32 -2
}
; iv | x < 100 ==> iv < 100 - x (signed)
define void @or_disjoint_signed(ptr %x_p) {
; CHECK-LABEL: define void @or_disjoint_signed
; CHECK-SAME: (ptr [[X_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nsw i32 100, [[X]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[EXIT:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
%x = load i32, ptr %x_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = or disjoint i32 %iv, %x
%x_check = icmp slt i32 %arith, 100
br i1 %x_check, label %exit, label %backedge
backedge:
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, 1000
br i1 %loop_cond, label %loop, label %exit
exit:
ret void
}
; iv | x < 100 ==> iv < 100 - x (unsigned)
define void @or_disjoint_unsigned(ptr %x_p) {
; CHECK-LABEL: define void @or_disjoint_unsigned
; CHECK-SAME: (ptr [[X_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG3]]
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = sub nuw i32 100, [[X]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp ult i32 [[IV]], [[INVARIANT_OP]]
; CHECK-NEXT: br i1 [[X_CHECK]], label [[EXIT:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
%x = load i32, ptr %x_p, !range !3
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = or disjoint i32 %iv, %x
%x_check = icmp ult i32 %arith, 100
br i1 %x_check, label %exit, label %backedge
backedge:
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp ult i32 %iv.next, 1000
br i1 %loop_cond, label %loop, label %exit
exit:
ret void
}
; Negative test: plain or (without disjoint) should NOT be hoisted.
define void @or_no_disjoint_neg(ptr %x_p) {
; CHECK-LABEL: define void @or_no_disjoint_neg
; CHECK-SAME: (ptr [[X_P:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[X_P]], align 4, !range [[RNG0]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: [[ARITH:%.*]] = or i32 [[IV]], [[X]]
; CHECK-NEXT: [[X_CHECK:%.*]] = icmp slt i32 [[ARITH]], 100
; CHECK-NEXT: br i1 [[X_CHECK]], label [[EXIT:%.*]], label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], 1000
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
%x = load i32, ptr %x_p, !range !0
br label %loop
loop:
%iv = phi i32 [0, %entry], [%iv.next, %backedge]
%arith = or i32 %iv, %x
%x_check = icmp slt i32 %arith, 100
br i1 %x_check, label %exit, label %backedge
backedge:
%iv.next = add nuw nsw i32 %iv, 4
%loop_cond = icmp slt i32 %iv.next, 1000
br i1 %loop_cond, label %loop, label %exit
exit:
ret void
}
!0 = !{i32 0, i32 2147483648}
!1 = !{i32 0, i32 2147483640}
!2 = !{i32 256, i32 32768}
!3 = !{i32 0, i32 2}
; The reassociation changes the icmp's LHS, so a samesign flag asserted about
; the original operands must be dropped (otherwise it can introduce poison).
define void @test_samesign_dropped(ptr %p, i32 %x) {
; CHECK-LABEL: define void @test_samesign_dropped
; CHECK-SAME: (ptr [[P:%.*]], i32 [[X:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[X]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[IV]], 95
; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[CMP]] to i32
; CHECK-NEXT: store volatile i32 [[SEL]], ptr [[P]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], 1
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i32 [[IV_NEXT]], 0
; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i32 [ %x, %entry ], [ %iv.next, %loop ]
%sum = add nsw i32 %iv, 5
%cmp = icmp samesign slt i32 %sum, 100
%sel = zext i1 %cmp to i32
store volatile i32 %sel, ptr %p
%iv.next = add nsw i32 %iv, 1
%done = icmp eq i32 %iv.next, 0
br i1 %done, label %exit, label %loop
exit:
ret void
}
Reference in new issue View Git Blame Copy Permalink