derek.holloway
7502bf64a4
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81 lines
2.9 KiB
LLVM
81 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -passes=licm -verify-memoryssa < %s | FileCheck %s
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define void @test(ptr %p) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[LOOP0:.*]]
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; CHECK: [[LOOP0]]:
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; CHECK-NEXT: br label %[[LOOP1:.*]]
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; CHECK: [[LOOP1]]:
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; CHECK-NEXT: [[DEC10:%.*]] = phi i64 [ 0, %[[LOOP0]] ], [ 1, %[[LOOP1]] ]
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; CHECK-NEXT: br i1 false, label %[[LOOP1_EXIT:.*]], label %[[LOOP1]]
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; CHECK: [[LOOP1_EXIT]]:
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; CHECK-NEXT: [[DEC10_LCSSA:%.*]] = phi i64 [ [[DEC10]], %[[LOOP1]] ]
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; CHECK-NEXT: switch i32 0, label %[[LOOP0_LATCH:.*]] [
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; CHECK-NEXT: i32 0, label %[[LOOP0_LATCH]]
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; CHECK-NEXT: i32 2, label %[[LOOP3_PREHEADER:.*]]
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; CHECK-NEXT: i32 1, label %[[LOOP2:.*]]
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; CHECK-NEXT: ]
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; CHECK: [[LOOP2]]:
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; CHECK-NEXT: br i1 false, label %[[LOOP0_LATCH]], label %[[LOOP3_PREHEADER]]
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; CHECK: [[LOOP3_PREHEADER]]:
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; CHECK-NEXT: br label %[[LOOP3:.*]]
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; CHECK: [[LOOP3]]:
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; CHECK-NEXT: switch i32 0, label %[[EXIT:.*]] [
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; CHECK-NEXT: i32 0, label %[[LOOP3]]
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; CHECK-NEXT: i32 1, label %[[LOOP2_LATCH:.*]]
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; CHECK-NEXT: ]
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; CHECK: [[LOOP2_LATCH]]:
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; CHECK-NEXT: br label %[[LOOP2]]
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; CHECK: [[LOOP0_LATCH]]:
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; CHECK-NEXT: br label %[[LOOP0]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[DEC10_LCSSA_LCSSA:%.*]] = phi i64 [ [[DEC10_LCSSA]], %[[LOOP3]] ]
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; CHECK-NEXT: store i64 [[DEC10_LCSSA_LCSSA]], ptr [[P]], align 4
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; CHECK-NEXT: store i64 1, ptr [[P]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop0
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loop0: ; preds = %loop0.latch, %entry
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br label %loop1
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loop1: ; preds = %loop1, %loop0
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%dec10 = phi i64 [ 0, %loop0 ], [ 1, %loop1 ]
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store i64 %dec10, ptr %p
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br i1 false, label %loop1.exit, label %loop1
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loop1.exit: ; preds = %loop1
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switch i32 0, label %loop0.latch [
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i32 0, label %loop0.latch
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i32 2, label %loop3.preheader
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i32 1, label %loop2
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]
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loop2: ; preds = %loop2.latch, %loop1.exit
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br i1 false, label %loop0.latch, label %loop3.preheader
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loop3.preheader: ; preds = %loop1.exit, %loop2
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br label %loop3
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loop3: ; preds = %loop3.preheader, %loop3
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switch i32 0, label %exit [
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i32 0, label %loop3
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i32 1, label %loop2.latch
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]
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loop2.latch: ; preds = %loop3
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br label %loop2
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loop0.latch: ; preds = %loop2, %loop1.exit, %loop1.exit
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store i64 0, ptr %p
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br label %loop0
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exit: ; preds = %loop3
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store i64 1, ptr %p
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ret void
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}
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