derek.holloway
7502bf64a4
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111 lines
4.8 KiB
LLVM
111 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=loop-interchange -cache-line-size=64 -S < %s | FileCheck %s
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; Test cases for PR43473.
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; In the 2 test cases below, we have a LCSSA PHI in the inner loop exit, which
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; is used in the outer loop latch. This is not supported.
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define void @test1(i1 %arg) {
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; CHECK-LABEL: define void @test1(
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; CHECK-SAME: i1 [[ARG:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
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; CHECK: [[OUTER_HEADER]]:
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; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ undef, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
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; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds double, ptr undef, i64 [[OUTER_IV]]
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; CHECK-NEXT: br label %[[INNER:.*]]
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; CHECK: [[INNER]]:
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; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[INNER_IV_NEXT:%.*]], %[[INNER]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[IDX]], align 8
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; CHECK-NEXT: store double undef, ptr [[IDX]], align 8
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; CHECK-NEXT: [[INNER_IV_NEXT]] = add nuw nsw i64 [[INNER_IV]], 1
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; CHECK-NEXT: br i1 [[ARG]], label %[[INNER]], label %[[OUTER_LATCH]]
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; CHECK: [[OUTER_LATCH]]:
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; CHECK-NEXT: [[INC43_LCSSA_WIDE_US:%.*]] = phi i64 [ [[INNER_IV_NEXT]], %[[INNER]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INC43_LCSSA_WIDE_US]] to i32
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; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
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; CHECK-NEXT: br i1 [[ARG]], label %[[OUTER_HEADER]], label %[[OUTER_EXIT:.*]]
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; CHECK: [[OUTER_EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %outer.header
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outer.header: ; preds = %for.cond26.for.end44_crit_edge.us, %entry
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%outer.iv = phi i64 [ undef, %entry ], [ %outer.iv.next, %outer.latch ]
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%idx = getelementptr inbounds double, ptr undef, i64 %outer.iv
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br label %inner
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inner: ; preds = %for.body28.us, %for.body25.us
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%inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
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%0 = load double, ptr %idx, align 8
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store double undef, ptr %idx, align 8
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%inner.iv.next = add nuw nsw i64 %inner.iv, 1
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br i1 %arg, label %inner, label %outer.latch
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outer.latch: ; preds = %inner
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%inc43.lcssa.wide.us = phi i64 [ %inner.iv.next, %inner ]
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%1 = trunc i64 %inc43.lcssa.wide.us to i32
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%outer.iv.next = add nsw i64 %outer.iv, 1
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br i1 %arg, label %outer.header, label %outer.exit
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outer.exit: ; preds = %for.cond26.for.end44_crit_edge.us
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ret void
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}
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; Same as @test1, but with a dedicated inner loop exit block.
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define void @test2(i1 %arg) {
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; CHECK-LABEL: define void @test2(
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; CHECK-SAME: i1 [[ARG:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
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; CHECK: [[OUTER_HEADER]]:
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; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ undef, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
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; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds double, ptr undef, i64 [[OUTER_IV]]
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; CHECK-NEXT: br label %[[INNER:.*]]
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; CHECK: [[INNER]]:
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; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[INNER_IV_NEXT:%.*]], %[[INNER]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[IDX]], align 8
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; CHECK-NEXT: store double undef, ptr [[IDX]], align 8
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; CHECK-NEXT: [[INNER_IV_NEXT]] = add nuw nsw i64 [[INNER_IV]], 1
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; CHECK-NEXT: br i1 [[ARG]], label %[[INNER]], label %[[INNER_EXIT:.*]]
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; CHECK: [[INNER_EXIT]]:
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; CHECK-NEXT: [[INC43_LCSSA_WIDE_US:%.*]] = phi i64 [ [[INNER_IV_NEXT]], %[[INNER]] ]
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; CHECK-NEXT: br label %[[OUTER_LATCH]]
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; CHECK: [[OUTER_LATCH]]:
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INC43_LCSSA_WIDE_US]] to i32
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; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
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; CHECK-NEXT: br i1 [[ARG]], label %[[OUTER_HEADER]], label %[[OUTER_EXIT:.*]]
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; CHECK: [[OUTER_EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %outer.header
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outer.header: ; preds = %for.cond26.for.end44_crit_edge.us, %entry
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%outer.iv = phi i64 [ undef, %entry ], [ %outer.iv.next, %outer.latch ]
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%idx = getelementptr inbounds double, ptr undef, i64 %outer.iv
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br label %inner
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inner: ; preds = %for.body28.us, %for.body25.us
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%inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
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%0 = load double, ptr %idx, align 8
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store double undef, ptr %idx, align 8
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%inner.iv.next = add nuw nsw i64 %inner.iv, 1
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br i1 %arg, label %inner, label %inner.exit
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inner.exit:
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%inc43.lcssa.wide.us = phi i64 [ %inner.iv.next, %inner ]
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br label %outer.latch
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outer.latch: ; preds = %inner
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%1 = trunc i64 %inc43.lcssa.wide.us to i32
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%outer.iv.next = add nsw i64 %outer.iv, 1
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br i1 %arg, label %outer.header, label %outer.exit
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outer.exit: ; preds = %for.cond26.for.end44_crit_edge.us
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ret void
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}
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