derek.holloway
7502bf64a4
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68 lines
2.9 KiB
LLVM
68 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=loop-reduce -S < %s | FileCheck %s
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target triple = "x86_64-unknown-linux-gnu"
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; Test that LSR doesn't create a chain of IV increments for instructions used only by llvm.assume.
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; The loop should keep a single IV with a +2 step rather than splitting into two +1 increments.
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define void @main(ptr %ptr) {
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; CHECK-LABEL: define void @main(
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; CHECK-SAME: ptr [[PTR:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[HEADER:.*]]
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; CHECK: [[HEADER]]:
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; CHECK-NEXT: [[TMP7:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[LATCH:.*]] ], [ 1, %[[ENTRY]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP7]], -1
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 10
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; CHECK-NEXT: call void @llvm.assume(i1 [[TMP3]])
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; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[TMP7]], 3
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; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[TMP4]]
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; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SCEVGEP2]], i64 -8
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; CHECK-NEXT: [[TMP5:%.*]] = load atomic i64, ptr [[SCEVGEP3]] unordered, align 8
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 0
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; CHECK-NEXT: br i1 [[TMP6]], label %[[EXIT:.*]], label %[[BODY:.*]]
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; CHECK: [[BODY]]:
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; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP7]], 10
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; CHECK-NEXT: call void @llvm.assume(i1 [[TMP8]])
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; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[TMP7]], 3
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[TMP9]]
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; CHECK-NEXT: [[TMP10:%.*]] = load atomic i64, ptr [[SCEVGEP1]] unordered, align 8
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[TMP10]], 0
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; CHECK-NEXT: br i1 [[TMP11]], label %[[EXIT]], label %[[LATCH]]
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; CHECK: [[LATCH]]:
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[TMP7]], 2
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; CHECK-NEXT: br label %[[HEADER]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %header
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header: ; preds = %latch, %entry
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%iv = phi i64 [ %iv.next, %latch ], [ 0, %entry ]
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%range_chk0 = icmp ult i64 %iv, 10
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call void @llvm.assume(i1 %range_chk0)
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%gep0 = getelementptr i64, ptr %ptr, i64 %iv
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%target0 = load atomic i64, ptr %gep0 unordered, align 8
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%check0 = icmp eq i64 %target0, 0
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br i1 %check0, label %exit, label %body
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body: ; preds = %header
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%iv.inc = add i64 %iv, 1
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%range_chk1 = icmp ult i64 %iv.inc, 10
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call void @llvm.assume(i1 %range_chk1)
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%gep1 = getelementptr i64, ptr %ptr, i64 %iv.inc
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%target1 = load atomic i64, ptr %gep1 unordered, align 8
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%check1 = icmp eq i64 %target1, 0
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br i1 %check1, label %exit, label %latch
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latch: ; preds = %bb4
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%iv.next = add nuw nsw i64 %iv, 2
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br label %header
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exit: ; preds = %bb4, %bb3, %body, %header
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ret void
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}
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declare void @llvm.assume(i1 noundef)
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