derek.holloway
7502bf64a4
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52 lines
2.0 KiB
LLVM
52 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=loop-reduce -S %s | FileCheck %s
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
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define i32 @test(i1 %c.1, ptr %src) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br i1 [[C_1:%.*]], label [[LOOP_LATCH]], label [[LOOP_THEN:%.*]]
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; CHECK: loop.then:
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[SRC:%.*]], align 4
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; CHECK-NEXT: [[C_2:%.*]] = icmp eq i32 [[L]], 0
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[P:%.*]] = phi i1 [ [[C_2]], [[LOOP_THEN]] ], [ false, [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[T:%.*]] = icmp sgt i32 [[LSR_IV]], -1050
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[P]], [[T]]
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; CHECK-NEXT: [[ZEXT_OR:%.*]] = zext i1 [[OR]] to i32
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw i32 [[LSR_IV]], 1
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; CHECK-NEXT: [[LOOP_HEADER_TERMCOND:%.*]] = icmp sgt i32 [[LSR_IV]], -1050
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; CHECK-NEXT: br i1 [[LOOP_HEADER_TERMCOND]], label [[LOOP_HEADER]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[ZEXT_OR_LCSSA:%.*]] = phi i32 [ [[ZEXT_OR]], [[LOOP_LATCH]] ]
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; CHECK-NEXT: ret i32 [[ZEXT_OR_LCSSA]]
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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br i1 %c.1, label %loop.latch, label %loop.then
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loop.then:
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%l = load i32, ptr %src
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%c.2 = icmp eq i32 %l, 0
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br label %loop.latch
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loop.latch:
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%p = phi i1 [ %c.2, %loop.then ], [ 0, %loop.header ]
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%t = icmp sgt i32 %iv, -1050
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%or = or i1 %p, %t
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%zext.or = zext i1 %or to i32
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%iv.next = add i32 %iv, %zext.or
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br i1 %t, label %loop.header, label %exit
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exit:
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ret i32 %zext.or
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}
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