derek.holloway
7502bf64a4
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142 lines
7.4 KiB
LLVM
142 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S | FileCheck %s
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; TODO: Move this test into tail-folding-iv-outside-user.ll
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define i32 @test(ptr %arr, i64 %n) {
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; CHECK-LABEL: define i32 @test(
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; CHECK-SAME: ptr [[ARR:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[N]], 1
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; CHECK-NEXT: br i1 [[CMP1]], label [[PREHEADER:%.*]], label [[DONE:%.*]]
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; CHECK: preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1
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; CHECK-NEXT: br label [[VECTOR_SCEVCHECK:%.*]]
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; CHECK: vector.scevcheck:
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[N]], -2
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; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP1]] to i8
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; CHECK-NEXT: [[TMP8:%.*]] = add i8 2, [[TMP7]]
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; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i8 [[TMP8]], 2
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; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP1]], 255
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; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP9]], [[TMP10]]
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; CHECK-NEXT: br i1 [[TMP12]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 3
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
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; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[TMP0]], 1
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 1, i64 2, i64 3, i64 4>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ]
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; CHECK-NEXT: [[VEC_IV:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT8:%.*]], [[PRED_STORE_CONTINUE8]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[TMP21:%.*]] = add nsw <4 x i64> [[VEC_IND]], splat (i64 -1)
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; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i1> [[TMP11]], i64 0
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; CHECK-NEXT: br i1 [[TMP24]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
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; CHECK: pred.store.if:
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; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i64> [[TMP21]], i64 0
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; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP17]]
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; CHECK-NEXT: store i32 65, ptr [[TMP18]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
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; CHECK: pred.store.continue:
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; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x i1> [[TMP11]], i64 1
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; CHECK-NEXT: br i1 [[TMP25]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
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; CHECK: pred.store.if2:
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; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i64> [[TMP21]], i64 1
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP13]]
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; CHECK-NEXT: store i32 65, ptr [[TMP14]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
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; CHECK: pred.store.continue3:
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; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP11]], i64 2
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; CHECK-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
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; CHECK: pred.store.if4:
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; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i64> [[TMP21]], i64 2
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; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP16]]
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; CHECK-NEXT: store i32 65, ptr [[TMP26]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
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; CHECK: pred.store.continue5:
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; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i1> [[TMP11]], i64 3
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; CHECK-NEXT: br i1 [[TMP27]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8]]
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; CHECK: pred.store.if6:
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; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i64> [[TMP21]], i64 3
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; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[TMP19]]
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; CHECK-NEXT: store i32 65, ptr [[TMP28]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
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; CHECK: pred.store.continue7:
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
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; CHECK-NEXT: [[VEC_IND_NEXT8]] = add nuw <4 x i64> [[VEC_IV]], splat (i64 4)
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; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP22:%.*]] = xor <4 x i1> [[TMP11]], splat (i1 true)
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; CHECK-NEXT: [[IND_END:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP22]], i1 false)
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; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[IND_END]], 1
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; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i64> [[VEC_IND]], i64 [[IND_ESCAPE]]
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; CHECK-NEXT: br label [[LOAD_VAL:%.*]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[CONV:%.*]] = phi i64 [ [[CONV2:%.*]], [[LOOP]] ], [ 1, [[SCALAR_PH]] ]
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; CHECK-NEXT: [[I:%.*]] = phi i8 [ [[INC:%.*]], [[LOOP]] ], [ 1, [[SCALAR_PH]] ]
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; CHECK-NEXT: [[SUB:%.*]] = add nsw i64 [[CONV]], -1
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[SUB]]
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; CHECK-NEXT: store i32 65, ptr [[PTR]], align 4
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; CHECK-NEXT: [[INC]] = add i8 [[I]], 1
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; CHECK-NEXT: [[CONV2]] = zext i8 [[INC]] to i64
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[CONV2]], [[N]]
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; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[LOAD_VAL]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: load_val:
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; CHECK-NEXT: [[FINAL:%.*]] = phi i64 [ [[CONV]], [[LOOP]] ], [ [[TMP23]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds i32, ptr [[ARR]], i64 [[FINAL]]
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; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[PTR2]], align 4
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; CHECK-NEXT: br label [[DONE]]
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; CHECK: done:
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; CHECK-NEXT: [[VALUE:%.*]] = phi i32 [ [[VAL]], [[LOAD_VAL]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[VALUE]]
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;
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entry:
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%cmp1 = icmp ugt i64 %n, 1
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br i1 %cmp1, label %preheader, label %done
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preheader:
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br label %loop
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loop:
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%conv = phi i64 [ %conv2, %loop ], [ 1, %preheader ]
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%i = phi i8 [ %inc, %loop ], [ 1, %preheader ]
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%sub = add nsw i64 %conv, -1
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%ptr = getelementptr inbounds i32, ptr %arr, i64 %sub
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store i32 65, ptr %ptr, align 4
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%inc = add i8 %i, 1
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%conv2 = zext i8 %inc to i64
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%cmp2 = icmp ult i64 %conv2, %n
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br i1 %cmp2, label %loop, label %load_val, !llvm.loop !0
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load_val:
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%final = phi i64 [ %conv, %loop ]
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%ptr2 = getelementptr inbounds i32, ptr %arr, i64 %final
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%val = load i32, ptr %ptr2, align 4
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br label %done
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done:
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%value = phi i32 [ %val, %load_val ], [ 0, %entry ]
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ret i32 %value
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}
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!0 = distinct !{!0, !1, !2, !3}
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!1 = !{!"llvm.loop.unroll.disable"}
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!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
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!3 = !{!"llvm.loop.vectorize.enable", i1 true}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"}
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; CHECK: [[META2]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
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;.
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