derek.holloway
7502bf64a4
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94 lines
4.9 KiB
LLVM
94 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -S %s | FileCheck --check-prefix=VF4IC2 %s
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; RUN: opt -p loop-vectorize -force-vector-width=8 -force-vector-interleave=1 -S %s | FileCheck --check-prefix=VF8IC1 %s
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; Test case from https://github.com/llvm/llvm-project/issues/153946.
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; %shr and thus %early.cond will be poison from %iv == 4 onwards.
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; Make sure the mask being poison does not propagate across lanes in the
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; OR reduction when computing the early exit condition in the vector loop.
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define noundef i32 @f(i32 noundef %g) {
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; VF4IC2-LABEL: define noundef i32 @f(
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; VF4IC2-SAME: i32 noundef [[G:%.*]]) {
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; VF4IC2-NEXT: [[ENTRY:.*:]]
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; VF4IC2-NEXT: br label %[[VECTOR_PH:.*]]
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; VF4IC2: [[VECTOR_PH]]:
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; VF4IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[G]], i64 0
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; VF4IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
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; VF4IC2-NEXT: br label %[[VECTOR_BODY:.*]]
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; VF4IC2: [[VECTOR_BODY]]:
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; VF4IC2-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 8, i32 16, i32 24>
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; VF4IC2-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[BROADCAST_SPLAT]], <i32 32, i32 40, i32 48, i32 56>
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; VF4IC2-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer
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; VF4IC2-NEXT: [[TMP5:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer
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; VF4IC2-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP4]]
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; VF4IC2-NEXT: [[TMP18:%.*]] = freeze <4 x i1> [[TMP5]]
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; VF4IC2-NEXT: [[TMP6:%.*]] = or <4 x i1> [[TMP17]], [[TMP18]]
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; VF4IC2-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
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; VF4IC2-NEXT: br i1 [[TMP7]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]
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; VF4IC2: [[MIDDLE_BLOCK]]:
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; VF4IC2-NEXT: br label %[[MIDDLE_BLOCK1:.*]]
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; VF4IC2: [[MIDDLE_BLOCK1]]:
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; VF4IC2-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP3]], i64 3
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; VF4IC2-NEXT: br label %[[RETURN:.*]]
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; VF4IC2: [[VECTOR_EARLY_EXIT]]:
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; VF4IC2-NEXT: [[TMP9:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP5]], i1 false)
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; VF4IC2-NEXT: [[TMP10:%.*]] = add i64 4, [[TMP9]]
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; VF4IC2-NEXT: [[TMP11:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP4]], i1 false)
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; VF4IC2-NEXT: [[TMP12:%.*]] = add i64 0, [[TMP11]]
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; VF4IC2-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP11]], 4
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; VF4IC2-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i64 [[TMP12]], i64 [[TMP10]]
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; VF4IC2-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32
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; VF4IC2-NEXT: br label %[[RETURN]]
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; VF4IC2: [[RETURN]]:
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; VF4IC2-NEXT: [[RES:%.*]] = phi i32 [ [[TMP8]], %[[MIDDLE_BLOCK1]] ], [ [[TMP15]], %[[VECTOR_EARLY_EXIT]] ]
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; VF4IC2-NEXT: ret i32 [[RES]]
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;
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; VF8IC1-LABEL: define noundef i32 @f(
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; VF8IC1-SAME: i32 noundef [[G:%.*]]) {
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; VF8IC1-NEXT: [[ENTRY:.*:]]
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; VF8IC1-NEXT: br label %[[VECTOR_PH:.*]]
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; VF8IC1: [[VECTOR_PH]]:
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; VF8IC1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[G]], i64 0
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; VF8IC1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer
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; VF8IC1-NEXT: br label %[[VECTOR_BODY:.*]]
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; VF8IC1: [[VECTOR_BODY]]:
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; VF8IC1-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 8, i32 16, i32 24, i32 32, i32 40, i32 48, i32 56>
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; VF8IC1-NEXT: [[TMP2:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer
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; VF8IC1-NEXT: [[TMP8:%.*]] = freeze <8 x i1> [[TMP2]]
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; VF8IC1-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP8]])
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; VF8IC1-NEXT: br i1 [[TMP3]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]
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; VF8IC1: [[MIDDLE_BLOCK]]:
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; VF8IC1-NEXT: br label %[[MIDDLE_BLOCK1:.*]]
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; VF8IC1: [[MIDDLE_BLOCK1]]:
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; VF8IC1-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP1]], i64 7
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; VF8IC1-NEXT: br label %[[RETURN:.*]]
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; VF8IC1: [[VECTOR_EARLY_EXIT]]:
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; VF8IC1-NEXT: [[TMP5:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> [[TMP2]], i1 false)
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; VF8IC1-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
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; VF8IC1-NEXT: br label %[[RETURN]]
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; VF8IC1: [[RETURN]]:
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; VF8IC1-NEXT: [[RES:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK1]] ], [ [[TMP6]], %[[VECTOR_EARLY_EXIT]] ]
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; VF8IC1-NEXT: ret i32 [[RES]]
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%mul = shl nuw nsw i32 %iv, 3
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%shr = ashr i32 %g, %mul
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%early.cond = icmp eq i32 %shr, 0
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br i1 %early.cond, label %loop.latch, label %return
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loop.latch:
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%iv.next = add nuw nsw i32 %iv, 1
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%ec = icmp eq i32 %iv.next, 8
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br i1 %ec, label %return, label %loop.header
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return:
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%res = phi i32 [ %shr, %loop.latch ], [ %iv, %loop.header ]
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ret i32 %res
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}
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