derek.holloway
7502bf64a4
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132 lines
4.0 KiB
LLVM
132 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=newgvn -enable-store-refinement -S | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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;; Both of these tests are tests of phi nodes that end up all equivalent to each other
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;; Without proper leader ordering, we will end up cycling the leader between all of them and never converge.
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define void @foo(i1 %arg, i1 %arg2) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ 1, [[BB18:%.*]] ]
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; CHECK-NEXT: br label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: br label [[BB4:%.*]]
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; CHECK: bb4:
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; CHECK-NEXT: br i1 [[ARG:%.*]], label [[BB18]], label [[BB7:%.*]]
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; CHECK: bb7:
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; CHECK-NEXT: br label [[BB9:%.*]]
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; CHECK: bb9:
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; CHECK-NEXT: br i1 [[ARG]], label [[BB2]], label [[BB11:%.*]]
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; CHECK: bb11:
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; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB16:%.*]], label [[BB14:%.*]]
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; CHECK: bb14:
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; CHECK-NEXT: br label [[BB4]]
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; CHECK: bb16:
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; CHECK-NEXT: br label [[BB7]]
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; CHECK: bb18:
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; CHECK-NEXT: br label [[BB1]]
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;
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bb:
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br label %bb1
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bb1: ; preds = %bb18, %bb
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%tmp = phi i32 [ 0, %bb ], [ 1, %bb18 ]
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br label %bb2
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bb2: ; preds = %bb9, %bb1
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%tmp3 = phi i32 [ %tmp, %bb1 ], [ %tmp8, %bb9 ]
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br label %bb4
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bb4: ; preds = %bb14, %bb2
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%tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp15, %bb14 ]
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br i1 %arg, label %bb18, label %bb7
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bb7: ; preds = %bb16, %bb4
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%tmp8 = phi i32 [ %tmp17, %bb16 ], [ %tmp5, %bb4 ]
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br label %bb9
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bb9: ; preds = %bb7
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br i1 %arg, label %bb2, label %bb11
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bb11: ; preds = %bb9
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br i1 %arg2, label %bb16, label %bb14
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bb14: ; preds = %bb11
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%tmp15 = phi i32 [ %tmp8, %bb11 ]
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br label %bb4
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bb16: ; preds = %bb11
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%tmp17 = phi i32 [ %tmp8, %bb11 ]
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br label %bb7
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bb18: ; preds = %bb4
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br label %bb1
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}
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%struct.a = type {}
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%struct.b = type {}
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declare void @c.d.p(i64, ptr)
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define void @e(i32 %a0, i32 %a1, ptr %p2) {
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; CHECK-LABEL: @e(
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; CHECK-NEXT: [[F:%.*]] = alloca i32, align 4
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; CHECK-NEXT: store i32 [[A0:%.*]], ptr [[F]], align 4, !g [[META0:![0-9]+]]
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; CHECK-NEXT: br label [[H:%.*]]
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; CHECK: h:
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; CHECK-NEXT: call void @c.d.p(i64 8, ptr undef)
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; CHECK-NEXT: [[I:%.*]] = load i32, ptr [[F]], align 4
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; CHECK-NEXT: [[J:%.*]] = load i32, ptr null, align 4
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; CHECK-NEXT: [[K:%.*]] = icmp eq i32 [[I]], [[J]]
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; CHECK-NEXT: br i1 [[K]], label [[L:%.*]], label [[Q:%.*]]
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; CHECK: l:
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; CHECK-NEXT: br label [[R:%.*]]
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; CHECK: q:
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; CHECK-NEXT: br label [[R]]
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; CHECK: r:
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; CHECK-NEXT: switch i32 undef, label [[N:%.*]] [
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; CHECK-NEXT: i32 0, label [[S:%.*]]
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; CHECK-NEXT: ]
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; CHECK: s:
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; CHECK-NEXT: store i32 [[A1:%.*]], ptr [[F]], align 4, !g [[META0]]
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; CHECK-NEXT: br label [[H]]
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; CHECK: n:
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; CHECK-NEXT: ret void
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;
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%f = alloca i32
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store i32 %a0, ptr %f, !g !0
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br label %h
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h: ; preds = %s, %0
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call void @c.d.p(i64 8, ptr undef)
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%i = load i32, ptr %f
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%j = load i32, ptr null
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%k = icmp eq i32 %i, %j
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br i1 %k, label %l, label %q
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l: ; preds = %h
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br label %r
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q: ; preds = %h
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%m = load ptr, ptr null
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br label %r
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r: ; preds = %q, %l
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switch i32 undef, label %n [
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i32 0, label %s
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]
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s: ; preds = %r
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store i32 %a1, ptr %f, !g !0
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br label %h
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n: ; preds = %r
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%o = load ptr, ptr %p2
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ret void
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}
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!0 = !{}
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