derek.holloway
7502bf64a4
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64 lines
3.4 KiB
LLVM
64 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
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; RUN: opt -passes='default<O3>' -S %s | FileCheck %s
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target triple = "arm64-apple-macosx"
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define void @mul3_clamp_u8_select(ptr noalias %out, ptr noalias %in) {
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; CHECK-LABEL: define void @mul3_clamp_u8_select(
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; CHECK-SAME: ptr noalias writeonly captures(none) [[OUT:%.*]], ptr noalias readonly captures(none) [[IN:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[VECTOR_PH:.*]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[IN]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 16
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP0]], align 1
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; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <16 x i8>, ptr [[TMP1]], align 1
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; CHECK-NEXT: [[TMP2:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i16>
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; CHECK-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[WIDE_LOAD2]] to <16 x i16>
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; CHECK-NEXT: [[TMP4:%.*]] = mul nuw nsw <16 x i16> [[TMP2]], splat (i16 3)
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; CHECK-NEXT: [[TMP5:%.*]] = mul nuw nsw <16 x i16> [[TMP3]], splat (i16 3)
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; CHECK-NEXT: [[TMP6:%.*]] = tail call <16 x i16> @llvm.umin.v16i16(<16 x i16> [[TMP4]], <16 x i16> splat (i16 255))
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; CHECK-NEXT: [[TMP7:%.*]] = tail call <16 x i16> @llvm.umin.v16i16(<16 x i16> [[TMP5]], <16 x i16> splat (i16 255))
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; CHECK-NEXT: [[TMP8:%.*]] = trunc nuw <16 x i16> [[TMP6]] to <16 x i8>
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; CHECK-NEXT: [[TMP9:%.*]] = trunc nuw <16 x i16> [[TMP7]] to <16 x i8>
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[OUT]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP10]], i64 16
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; CHECK-NEXT: store <16 x i8> [[TMP8]], ptr [[TMP10]], align 1
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; CHECK-NEXT: store <16 x i8> [[TMP9]], ptr [[TMP11]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 992
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; CHECK-NEXT: br i1 [[TMP12]], label %[[VEC_EPILOG_VECTOR_BODY:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[VEC_EPILOG_VECTOR_BODY]]:
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw i8, ptr [[IN]], i64 992
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; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <8 x i8>, ptr [[TMP13]], align 1
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; CHECK-NEXT: [[TMP14:%.*]] = zext <8 x i8> [[WIDE_LOAD6]] to <8 x i16>
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; CHECK-NEXT: [[TMP15:%.*]] = mul nuw nsw <8 x i16> [[TMP14]], splat (i16 3)
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; CHECK-NEXT: [[TMP16:%.*]] = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> [[TMP15]], <8 x i16> splat (i16 255))
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; CHECK-NEXT: [[TMP17:%.*]] = trunc nuw <8 x i16> [[TMP16]] to <8 x i8>
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; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw i8, ptr [[OUT]], i64 992
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; CHECK-NEXT: store <8 x i8> [[TMP17]], ptr [[TMP18]], align 1
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%i = phi i64 [0, %entry], [%inc, %loop]
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%pi = getelementptr inbounds i8, ptr %in, i64 %i
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%vi = load i8, ptr %pi, align 1
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%z = zext i8 %vi to i32
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%m = mul nuw nsw i32 %z, 3
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%cmp = icmp ugt i32 %m, 255
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%sel = select i1 %cmp, i32 255, i32 %m
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%t = trunc i32 %sel to i8
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%po = getelementptr inbounds i8, ptr %out, i64 %i
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store i8 %t, ptr %po, align 1
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%inc = add nuw i64 %i, 1
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%ex = icmp eq i64 %inc, 1000
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br i1 %ex, label %exit, label %loop
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exit:
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ret void
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}
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