derek.holloway
7502bf64a4
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271 lines
14 KiB
LLVM
271 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes="default<O1>" -S < %s | FileCheck --check-prefixes=O1 %s
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; RUN: opt -passes="default<O2>" -S < %s | FileCheck --check-prefixes=O2 %s
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; RUN: opt -passes="default<O3>" -S < %s | FileCheck --check-prefixes=O3 %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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%"class.std::vector" = type { %"struct.std::_Vector_base" }
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%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
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%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
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%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
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$_ZNSt6vectorIiSaIiEEixEm = comdat any
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define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(ptr noundef nonnull align 8 dereferenceable(24) %data, i64 noundef %numElems) {
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; O1-LABEL: define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(
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; O1-SAME: ptr noundef nonnull readonly align 8 captures(none) dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; O1-NEXT: [[ENTRY:.*]]:
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; O1-NEXT: [[CMP24_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
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; O1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DATA]], align 8
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; O1-NEXT: br label %[[FOR_COND1_PREHEADER:.*]]
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; O1: [[FOR_COND1_PREHEADER]]:
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; O1-NEXT: [[I_06:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INC7:%.*]], %[[FOR_COND_CLEANUP3:.*]] ]
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; O1-NEXT: br i1 [[CMP24_NOT]], label %[[FOR_COND_CLEANUP3]], label %[[FOR_BODY4:.*]]
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; O1: [[FOR_COND_CLEANUP:.*]]:
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; O1-NEXT: ret void
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; O1: [[FOR_COND_CLEANUP3]]:
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; O1-NEXT: [[INC7]] = add nuw nsw i64 [[I_06]], 1
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; O1-NEXT: [[EXITCOND7_NOT:%.*]] = icmp eq i64 [[INC7]], 100
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; O1-NEXT: br i1 [[EXITCOND7_NOT]], label %[[FOR_COND_CLEANUP]], label %[[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]
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; O1: [[FOR_BODY4]]:
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; O1-NEXT: [[J_05:%.*]] = phi i64 [ [[INC5:%.*]], %[[FOR_BODY4]] ], [ 0, %[[FOR_COND1_PREHEADER]] ]
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; O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP0]], i64 [[J_05]]
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; O1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ADD_PTR_I]], align 4, !tbaa [[INT_TBAA2:![0-9]+]]
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; O1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
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; O1-NEXT: store i32 [[INC]], ptr [[ADD_PTR_I]], align 4, !tbaa [[INT_TBAA2]]
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; O1-NEXT: [[INC5]] = add nuw i64 [[J_05]], 1
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; O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]]
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; O1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP3]], label %[[FOR_BODY4]], !llvm.loop [[LOOP6:![0-9]+]]
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;
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; O2-LABEL: define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(
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; O2-SAME: ptr noundef nonnull readonly align 8 captures(none) dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; O2-NEXT: [[ENTRY:.*]]:
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; O2-NEXT: [[CMP24_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
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; O2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DATA]], align 8
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; O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8
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; O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8
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; O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[NUMELEMS]], [[N_VEC]]
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; O2-NEXT: br label %[[FOR_COND1_PREHEADER:.*]]
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; O2: [[FOR_COND1_PREHEADER]]:
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; O2-NEXT: [[I_06:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INC7:%.*]], %[[FOR_COND_CLEANUP3:.*]] ]
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; O2-NEXT: br i1 [[CMP24_NOT]], label %[[FOR_COND_CLEANUP3]], label %[[FOR_BODY4_PREHEADER:.*]]
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; O2: [[FOR_BODY4_PREHEADER]]:
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; O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[FOR_BODY4_PREHEADER9:.*]], label %[[VECTOR_BODY:.*]]
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; O2: [[VECTOR_BODY]]:
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; O2-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ], [ 0, %[[FOR_BODY4_PREHEADER]] ]
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; O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP0]], i64 [[INDEX]]
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; O2-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 16
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; O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4, !tbaa [[INT_TBAA0:![0-9]+]]
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; O2-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4, !tbaa [[INT_TBAA0]]
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; O2-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], splat (i32 1)
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; O2-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[WIDE_LOAD8]], splat (i32 1)
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; O2-NEXT: store <4 x i32> [[TMP3]], ptr [[TMP1]], align 4, !tbaa [[INT_TBAA0]]
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; O2-NEXT: store <4 x i32> [[TMP4]], ptr [[TMP2]], align 4, !tbaa [[INT_TBAA0]]
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; O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; O2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; O2-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; O2: [[MIDDLE_BLOCK]]:
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; O2-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP3]], label %[[FOR_BODY4_PREHEADER9]]
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; O2: [[FOR_BODY4_PREHEADER9]]:
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; O2-NEXT: [[J_05_PH:%.*]] = phi i64 [ 0, %[[FOR_BODY4_PREHEADER]] ], [ [[N_VEC]], %[[MIDDLE_BLOCK]] ]
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; O2-NEXT: br label %[[FOR_BODY4:.*]]
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; O2: [[FOR_COND_CLEANUP:.*]]:
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; O2-NEXT: ret void
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; O2: [[FOR_COND_CLEANUP3]]:
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; O2-NEXT: [[INC7]] = add nuw nsw i64 [[I_06]], 1
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; O2-NEXT: [[EXITCOND7_NOT:%.*]] = icmp eq i64 [[INC7]], 100
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; O2-NEXT: br i1 [[EXITCOND7_NOT]], label %[[FOR_COND_CLEANUP]], label %[[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP8:![0-9]+]]
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; O2: [[FOR_BODY4]]:
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; O2-NEXT: [[J_05:%.*]] = phi i64 [ [[INC5:%.*]], %[[FOR_BODY4]] ], [ [[J_05_PH]], %[[FOR_BODY4_PREHEADER9]] ]
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; O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP0]], i64 [[J_05]]
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; O2-NEXT: [[TMP6:%.*]] = load i32, ptr [[ADD_PTR_I]], align 4, !tbaa [[INT_TBAA0]]
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; O2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
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; O2-NEXT: store i32 [[INC]], ptr [[ADD_PTR_I]], align 4, !tbaa [[INT_TBAA0]]
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; O2-NEXT: [[INC5]] = add nuw i64 [[J_05]], 1
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; O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]]
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; O2-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP3]], label %[[FOR_BODY4]], !llvm.loop [[LOOP9:![0-9]+]]
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;
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; O3-LABEL: define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(
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; O3-SAME: ptr noundef nonnull readonly align 8 captures(none) dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; O3-NEXT: [[ENTRY:.*:]]
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; O3-NEXT: [[CMP24_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
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; O3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DATA]], align 8
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; O3-NEXT: br i1 [[CMP24_NOT]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_COND1_PREHEADER_US_PREHEADER:.*]]
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; O3: [[FOR_COND1_PREHEADER_US_PREHEADER]]:
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; O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8
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; O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8
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; O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[NUMELEMS]], [[N_VEC]]
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; O3-NEXT: br label %[[FOR_COND1_PREHEADER_US:.*]]
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; O3: [[FOR_COND1_PREHEADER_US]]:
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; O3-NEXT: [[I_06_US:%.*]] = phi i64 [ [[INC7_US:%.*]], %[[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:.*]] ], [ 0, %[[FOR_COND1_PREHEADER_US_PREHEADER]] ]
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; O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[FOR_BODY4_US_PREHEADER:.*]], label %[[VECTOR_BODY:.*]]
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; O3: [[VECTOR_BODY]]:
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; O3-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ], [ 0, %[[FOR_COND1_PREHEADER_US]] ]
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; O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP0]], i64 [[INDEX]]
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; O3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 16
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; O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4, !tbaa [[INT_TBAA0:![0-9]+]]
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; O3-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4, !tbaa [[INT_TBAA0]]
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; O3-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], splat (i32 1)
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; O3-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[WIDE_LOAD9]], splat (i32 1)
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; O3-NEXT: store <4 x i32> [[TMP3]], ptr [[TMP1]], align 4, !tbaa [[INT_TBAA0]]
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; O3-NEXT: store <4 x i32> [[TMP4]], ptr [[TMP2]], align 4, !tbaa [[INT_TBAA0]]
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; O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; O3-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; O3-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; O3: [[MIDDLE_BLOCK]]:
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; O3-NEXT: br i1 [[CMP_N]], label %[[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label %[[FOR_BODY4_US_PREHEADER]]
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; O3: [[FOR_BODY4_US_PREHEADER]]:
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; O3-NEXT: [[J_05_US_PH:%.*]] = phi i64 [ 0, %[[FOR_COND1_PREHEADER_US]] ], [ [[N_VEC]], %[[MIDDLE_BLOCK]] ]
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; O3-NEXT: br label %[[FOR_BODY4_US:.*]]
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; O3: [[FOR_BODY4_US]]:
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; O3-NEXT: [[J_05_US:%.*]] = phi i64 [ [[INC5_US:%.*]], %[[FOR_BODY4_US]] ], [ [[J_05_US_PH]], %[[FOR_BODY4_US_PREHEADER]] ]
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; O3-NEXT: [[ADD_PTR_I_US:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP0]], i64 [[J_05_US]]
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; O3-NEXT: [[TMP6:%.*]] = load i32, ptr [[ADD_PTR_I_US]], align 4, !tbaa [[INT_TBAA0]]
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; O3-NEXT: [[INC_US:%.*]] = add nsw i32 [[TMP6]], 1
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; O3-NEXT: store i32 [[INC_US]], ptr [[ADD_PTR_I_US]], align 4, !tbaa [[INT_TBAA0]]
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; O3-NEXT: [[INC5_US]] = add nuw i64 [[J_05_US]], 1
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; O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5_US]], [[NUMELEMS]]
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; O3-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label %[[FOR_BODY4_US]], !llvm.loop [[LOOP8:![0-9]+]]
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; O3: [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]]:
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; O3-NEXT: [[INC7_US]] = add nuw nsw i64 [[I_06_US]], 1
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; O3-NEXT: [[EXITCOND8_NOT:%.*]] = icmp eq i64 [[INC7_US]], 100
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; O3-NEXT: br i1 [[EXITCOND8_NOT]], label %[[FOR_COND_CLEANUP]], label %[[FOR_COND1_PREHEADER_US]], !llvm.loop [[LOOP9:![0-9]+]]
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; O3: [[FOR_COND_CLEANUP]]:
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; O3-NEXT: ret void
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;
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entry:
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%data.addr = alloca ptr, align 8
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%numElems.addr = alloca i64, align 8
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%i = alloca i64, align 8
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%cleanup.dest.slot = alloca i32, align 4
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%j = alloca i64, align 8
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store ptr %data, ptr %data.addr, align 8, !tbaa !3
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store i64 %numElems, ptr %numElems.addr, align 8, !tbaa !7
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call void @llvm.lifetime.start.p0(ptr %i)
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store i64 0, ptr %i, align 8, !tbaa !7
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br label %for.cond
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for.cond:
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%0 = load i64, ptr %i, align 8, !tbaa !7
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%cmp = icmp ult i64 %0, 100
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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store i32 2, ptr %cleanup.dest.slot, align 4
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call void @llvm.lifetime.end.p0(ptr %i)
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br label %for.end8
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for.body:
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call void @llvm.lifetime.start.p0(ptr %j)
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store i64 0, ptr %j, align 8, !tbaa !7
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br label %for.cond1
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for.cond1:
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%1 = load i64, ptr %j, align 8, !tbaa !7
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%2 = load i64, ptr %numElems.addr, align 8, !tbaa !7
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%cmp2 = icmp ult i64 %1, %2
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br i1 %cmp2, label %for.body4, label %for.cond.cleanup3
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for.cond.cleanup3:
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store i32 5, ptr %cleanup.dest.slot, align 4
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call void @llvm.lifetime.end.p0(ptr %j)
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br label %for.end
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for.body4:
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%3 = load ptr, ptr %data.addr, align 8, !tbaa !3
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%4 = load i64, ptr %j, align 8, !tbaa !7
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%call = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %4)
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%5 = load i32, ptr %call, align 4, !tbaa !9
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%inc = add nsw i32 %5, 1
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store i32 %inc, ptr %call, align 4, !tbaa !9
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br label %for.inc
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for.inc:
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%6 = load i64, ptr %j, align 8, !tbaa !7
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%inc5 = add i64 %6, 1
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store i64 %inc5, ptr %j, align 8, !tbaa !7
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br label %for.cond1, !llvm.loop !11
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for.end:
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br label %for.inc6
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for.inc6:
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%7 = load i64, ptr %i, align 8, !tbaa !7
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%inc7 = add i64 %7, 1
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store i64 %inc7, ptr %i, align 8, !tbaa !7
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br label %for.cond, !llvm.loop !13
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for.end8:
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ret void
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}
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declare void @llvm.lifetime.start.p0(ptr nocapture)
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define linkonce_odr dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %this, i64 noundef %__n) comdat align 2 {
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entry:
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%this.addr = alloca ptr, align 8
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%__n.addr = alloca i64, align 8
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store ptr %this, ptr %this.addr, align 8, !tbaa !3
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store i64 %__n, ptr %__n.addr, align 8, !tbaa !14
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%this1 = load ptr, ptr %this.addr, align 8
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%_M_start = getelementptr inbounds %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data", ptr %this1, i32 0, i32 0
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%0 = load ptr, ptr %_M_start, align 8, !tbaa !16
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%1 = load i64, ptr %__n.addr, align 8, !tbaa !14
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%add.ptr = getelementptr inbounds i32, ptr %0, i64 %1
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ret ptr %add.ptr
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}
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declare void @llvm.lifetime.end.p0(ptr nocapture)
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"uwtable", i32 2}
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!2 = !{!"clang version 15.0.0 (https://github.com/llvm/llvm-project.git 69297cf639044acf48dd5d9b39b95c54dd50561d)"}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"any pointer", !5, i64 0}
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!5 = !{!"omnipotent char", !6, i64 0}
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!6 = !{!"Simple C++ TBAA"}
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!7 = !{!8, !8, i64 0}
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!8 = !{!"long long", !5, i64 0}
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!9 = !{!10, !10, i64 0}
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!10 = !{!"int", !5, i64 0}
|
|
!11 = distinct !{!11, !12}
|
|
!12 = !{!"llvm.loop.mustprogress"}
|
|
!13 = distinct !{!13, !12}
|
|
!14 = !{!15, !15, i64 0}
|
|
!15 = !{!"long", !5, i64 0}
|
|
!16 = !{!17, !4, i64 0}
|
|
!17 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !4, i64 0, !4, i64 8, !4, i64 16}
|
|
;.
|
|
; O1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}
|
|
; O1: [[META1]] = !{!"llvm.loop.mustprogress"}
|
|
; O1: [[INT_TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
|
|
; O1: [[META3]] = !{!"int", [[META4:![0-9]+]], i64 0}
|
|
; O1: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
|
|
; O1: [[META5]] = !{!"Simple C++ TBAA"}
|
|
; O1: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]]}
|
|
;.
|
|
; O2: [[INT_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
|
|
; O2: [[META1]] = !{!"int", [[META2:![0-9]+]], i64 0}
|
|
; O2: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]], i64 0}
|
|
; O2: [[META3]] = !{!"Simple C++ TBAA"}
|
|
; O2: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]], [[META6:![0-9]+]], [[META7:![0-9]+]]}
|
|
; O2: [[META5]] = !{!"llvm.loop.mustprogress"}
|
|
; O2: [[META6]] = !{!"llvm.loop.isvectorized", i32 1}
|
|
; O2: [[META7]] = !{!"llvm.loop.unroll.runtime.disable"}
|
|
; O2: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]}
|
|
; O2: [[LOOP9]] = distinct !{[[LOOP9]], [[META5]], [[META7]], [[META6]]}
|
|
;.
|
|
; O3: [[INT_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
|
|
; O3: [[META1]] = !{!"int", [[META2:![0-9]+]], i64 0}
|
|
; O3: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]], i64 0}
|
|
; O3: [[META3]] = !{!"Simple C++ TBAA"}
|
|
; O3: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]], [[META6:![0-9]+]], [[META7:![0-9]+]]}
|
|
; O3: [[META5]] = !{!"llvm.loop.mustprogress"}
|
|
; O3: [[META6]] = !{!"llvm.loop.isvectorized", i32 1}
|
|
; O3: [[META7]] = !{!"llvm.loop.unroll.runtime.disable"}
|
|
; O3: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]], [[META7]], [[META6]]}
|
|
; O3: [[LOOP9]] = distinct !{[[LOOP9]], [[META5]]}
|
|
;.
|