derek.holloway
7502bf64a4
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77 lines
2.7 KiB
LLVM
77 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx12.0.0"
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define i32 @f(i32 noundef %x) {
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; CHECK-LABEL: define range(i32 0, 2) i32 @f(
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; CHECK-SAME: i32 noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 8
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; CHECK-NEXT: br i1 [[TMP0]], label %[[SWITCH_LOOKUP:.*]], label %[[SW_EPILOG:.*]]
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; CHECK: [[SWITCH_LOOKUP]]:
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; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[X]] to i64
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; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds nuw [4 x i8], ptr @switch.table.g, i64 [[TMP1]]
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; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
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; CHECK-NEXT: br label %[[SW_EPILOG]]
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; CHECK: [[SW_EPILOG]]:
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; CHECK-NEXT: [[X_ADDR_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], %[[SWITCH_LOOKUP]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: ret i32 [[X_ADDR_0]]
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;
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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switch i32 %0, label %sw.default [
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i32 0, label %sw.bb
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i32 2, label %sw.bb
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i32 4, label %sw.bb
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i32 6, label %sw.bb
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i32 7, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
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store i32 1, ptr %x.addr, align 4
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br label %sw.epilog
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sw.default: ; preds = %entry
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store i32 0, ptr %x.addr, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.default, %sw.bb
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%1 = load i32, ptr %x.addr, align 4
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ret i32 %1
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}
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define i32 @g(i32 noundef %x) {
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; CHECK-LABEL: define range(i32 0, 2) i32 @g(
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; CHECK-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] {
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; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]]
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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switch i32 %0, label %sw.default [
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i32 0, label %sw.bb
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i32 2, label %sw.bb
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i32 4, label %sw.bb
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i32 6, label %sw.bb
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i32 7, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
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store i32 1, ptr %x.addr, align 4
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br label %sw.epilog
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sw.default: ; preds = %entry
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store i32 0, ptr %x.addr, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.default, %sw.bb
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%1 = load i32, ptr %x.addr, align 4
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ret i32 %1
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}
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