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TheRock/compiler/amd-llvm/llvm/test/Transforms/Reassociate/cse-pairs.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

84 lines
3.3 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=reassociate,early-cse -earlycse-debug-hash -S < %s | FileCheck %s
@num1 = local_unnamed_addr global i32 0, align 4
@num2 = local_unnamed_addr global i32 0, align 4
@num3 = local_unnamed_addr global i32 0, align 4
@num4 = local_unnamed_addr global i32 0, align 4
define signext i32 @twoPairs(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3, i32 signext %4) {
; CHECK-LABEL: @twoPairs(
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP2:%.*]], [[TMP0:%.*]]
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP1:%.*]]
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP3:%.*]]
; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], [[TMP4:%.*]]
; CHECK-NEXT: store i32 [[TMP9]], ptr @num1, align 4
; CHECK-NEXT: store i32 [[TMP6]], ptr @num2, align 4
; CHECK-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP3]], [[TMP1]]
; CHECK-NEXT: store i32 [[TMP10]], ptr @num3, align 4
; CHECK-NEXT: ret i32 undef
;
%6 = add i32 %2, %0
%7 = add i32 %6, %1
%8 = add i32 %7, %3
%9 = add i32 %8, %4
store i32 %9, ptr @num1, align 4
%10 = add nsw i32 %2, %0
store i32 %10, ptr @num2, align 4
%11 = add nsw i32 %3, %1
store i32 %11, ptr @num3, align 4
ret i32 undef
}
define signext i32 @twoPairsAllOpInPairs(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: @twoPairsAllOpInPairs(
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP2:%.*]], [[TMP1:%.*]]
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], [[TMP0:%.*]]
; CHECK-NEXT: [[TMP7:%.*]] = add nsw i32 [[TMP6]], [[TMP3:%.*]]
; CHECK-NEXT: store i32 [[TMP7]], ptr @num1, align 4
; CHECK-NEXT: store i32 [[TMP5]], ptr @num2, align 4
; CHECK-NEXT: [[TMP8:%.*]] = add nsw i32 [[TMP3]], [[TMP0]]
; CHECK-NEXT: store i32 [[TMP8]], ptr @num3, align 4
; CHECK-NEXT: ret i32 undef
;
%5 = add nsw i32 %0, %1
%6 = add nsw i32 %5, %2
%7 = add nsw i32 %6, %3
store i32 %7, ptr @num1, align 4
%8 = add nsw i32 %1, %2
store i32 %8, ptr @num2, align 4
%9 = add nsw i32 %0, %3
store i32 %9, ptr @num3, align 4
ret i32 undef
}
define signext i32 @threePairsAllOpInPairs(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3, i32 signext %4, i32 signext %5) {
; CHECK-LABEL: @threePairsAllOpInPairs(
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP3:%.*]], [[TMP2:%.*]]
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP0:%.*]]
; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], [[TMP1:%.*]]
; CHECK-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP9]], [[TMP4:%.*]]
; CHECK-NEXT: [[TMP11:%.*]] = add nsw i32 [[TMP10]], [[TMP5:%.*]]
; CHECK-NEXT: store i32 [[TMP11]], ptr @num1, align 4
; CHECK-NEXT: [[TMP12:%.*]] = add nsw i32 [[TMP5]], [[TMP0]]
; CHECK-NEXT: store i32 [[TMP12]], ptr @num2, align 4
; CHECK-NEXT: [[TMP13:%.*]] = add nsw i32 [[TMP4]], [[TMP1]]
; CHECK-NEXT: store i32 [[TMP13]], ptr @num3, align 4
; CHECK-NEXT: store i32 [[TMP7]], ptr @num4, align 4
; CHECK-NEXT: ret i32 undef
;
%7 = add nsw i32 %0, %1
%8 = add nsw i32 %7, %2
%9 = add nsw i32 %8, %3
%10 = add nsw i32 %9, %4
%11 = add nsw i32 %10, %5
store i32 %11, ptr @num1, align 4
%12 = add nsw i32 %0, %5
store i32 %12, ptr @num2, align 4
%13 = add nsw i32 %1, %4
store i32 %13, ptr @num3, align 4
%14 = add nsw i32 %2, %3
store i32 %14, ptr @num4, align 4
ret i32 undef
}