derek.holloway
7502bf64a4
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53 lines
2.4 KiB
LLVM
53 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64-unknown-linux -mattr=+v -slp-threshold=-100 | FileCheck %s --check-prefix=RISCV
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; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux -slp-threshold=-100 | FileCheck %s
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; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=aarch64-unknown-linux -slp-threshold=-100 | FileCheck %s
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; REQUIRES: aarch64-registered-target, x86-registered-target, riscv-registered-target
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define i64 @test(ptr %p) {
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; RISCV-LABEL: @test(
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; RISCV-NEXT: entry:
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; RISCV-NEXT: [[TMP0:%.*]] = load <6 x i64>, ptr [[P:%.*]], align 4
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; RISCV-NEXT: [[TMP4:%.*]] = shufflevector <6 x i64> [[TMP0]], <6 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 0, i32 0>
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; RISCV-NEXT: [[TMP5:%.*]] = mul <8 x i64> [[TMP4]], splat (i64 42)
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; RISCV-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[TMP5]])
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; RISCV-NEXT: ret i64 [[TMP6]]
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;
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <6 x i64>, ptr [[P:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <6 x i64> [[TMP0]], <6 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 0, i32 0>
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; CHECK-NEXT: [[TMP2:%.*]] = mul <8 x i64> [[TMP1]], splat (i64 42)
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; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[TMP2]])
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; CHECK-NEXT: ret i64 [[TMP3]]
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;
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entry:
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%arrayidx.1 = getelementptr inbounds i64, ptr %p, i64 1
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%arrayidx.2 = getelementptr inbounds i64, ptr %p, i64 2
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%arrayidx.3 = getelementptr inbounds i64, ptr %p, i64 3
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%arrayidx.4 = getelementptr inbounds i64, ptr %p, i64 4
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%arrayidx.5 = getelementptr inbounds i64, ptr %p, i64 5
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%tmp = load i64, ptr %p, align 4
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%mul = mul i64 %tmp, 42
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%tmp1 = load i64, ptr %arrayidx.1, align 4
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%mul1 = mul i64 %tmp1, 42
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%add = add i64 %mul, %mul1
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%tmp2 = load i64, ptr %arrayidx.2, align 4
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%mul2 = mul i64 %tmp2, 42
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%add1 = add i64 %add, %mul2
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%tmp3 = load i64, ptr %arrayidx.3, align 4
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%mul3 = mul i64 %tmp3, 42
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%add2 = add i64 %add1, %mul3
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%tmp4 = load i64, ptr %arrayidx.4, align 4
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%mul4 = mul i64 %tmp4, 42
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%add3 = add i64 %add2, %mul4
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%tmp5 = load i64, ptr %arrayidx.5, align 4
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%mul5 = mul i64 %tmp5, 42
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%add4 = add i64 %add3, %mul5
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%mul6 = mul i64 %tmp, 42
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%add5 = add i64 %add4, %mul6
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%mul7 = mul i64 %tmp, 42
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%add6 = add i64 %add5, %mul7
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ret i64 %add6
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}
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